DS3991
Low-Cost CCFL Controller
_______________________________________________________________________________________ 7
Main System Block Diagram
GA
GB
OVD
OVERVOLTAGE
DETECTION
LCM
LAMP CURRENT
MONITOR
80Hz TO 300Hz
EXTERNAL RESISTOR
LAMP FREQUENCY SET
VCC (4.5V TO 5.5V)
GND
CCFL
CONTROLLER
(SEE THE
CCFL CHANNEL
BLOCK
DIAGRAM)
EXTERNAL RESISTOR
BURST-DIMMING
FREQUENCY SET
ANALOG LAMP
BRIGHTNESS CONTROL
(PWM_EN = 0)
PWM LAMP
BRIGHTNESS CONTROL
(PWM_EN = 1)
SVML
SUPPLY VOLTAGE
MONITOR LOW
CHANNEL FAULT
CHANNEL ENABLE
MOSFET
GATE DRIVERS
LOSC
PWM_EN
BRIGHT
SLOPE
POSC
DPWM
SIGNAL
2.0V
40kHz TO 80kHz
OSCILLATOR (±5%)
80Hz TO 300Hz
OSCILLATOR (±5%)
POSITIVE OR
NEGATIVE SLOPE
SELECT
RAMP
GENERATOR
FAULT
HANDLING
SYSTEM
ENABLE/
POR
MUX
SVMH
SUPPLY VOLTAGE
MONITOR HIGH
2.0V
VREF
UVLO
DS3991
DS3991
Low-Cost CCFL Controller
8 _______________________________________________________________________________________
CCFL Channel Block Diagram
GATE
DRIVERS
GA
GB
DIGITAL
CCFL
CONTROLLER
CHANNEL FAULT
LAMP FREQUENCY
(40kHz TO 80kHz)
BURST-DIMMING
PWM SIGNAL
CHANNEL ENABLE
MOSFET
GATE DRIVERS
LCM
LAMP CURRENT MONITOR
400mV
2.0V
LAMP OVERCURRENT
LAMP STRIKE AND REGULATION
LAMP OUT
1.0V
1.0V
OVD
OVERVOLTAGE DETECTOR
LAMP MAXIMUM VOLTAGE REGULATION
64 LAMP CYCLE
INTEGRATOR
OVERVOLTAGE
DS3991
Detailed Description
The DS3991 is available for both push-pull and half-
bridge drive topologies. In both drive topologies, the
DS3991 drives two logic-level MOSFETs. The DS3991
alternately turns on the two MOSFETs to create the high-
voltage AC waveform on the secondary. By varying the
duration of the MOSFET turn-on times, the controller is
able to accurately control the amount of current flowing
through the CCFL lamp. See the
Typical Push-Pull
Application
and
Typical Half-Bridge Application
figures.
The DS3991 can also drive more than one CCFL lamp
per channel. The
Typical Push-Pull Application, Multiple
Lamps Per Channel
and
Typical Half-Bridge Application,
Multiple Lamps Per Channel
figures show an application
driving three lamps.
A series resistor on the low-voltage side of the CCFL
lamp enables current monitoring. The voltage developed
across this resistor is fed to the lamp current monitor
(LCM) input on the DS3991. The DS3991 compares the
resistor voltage against an internal reference voltage to
determine the duty cycle for the MOSFET gates. See the
Main System Block Diagram
and the
CCFL Channel
Block Diagram
for more information.
Dimming Control
The DS3991 uses burst dimming to control the lamp
brightness. During the high period of the DPWM cycle,
the lamp is driven at the selected lamp frequency
(40kHz to 80kHz) as shown in Figure 1. This part of the
cycle is also called the burst period because of the
lamp-frequency burst that occurs during this time.
During the low period of the DPWM cycle, the controller
disables the MOSFET gate drivers so the lamp is not
driven. This causes the current to stop flowing in the
lamp, but the time is short enough to keep the lamp
from de-ionizing. Dimming is increased/decreased by
adjusting (i.e., modulating) the burst-period duty cycle.
At the beginning of each burst-dimming cycle, soft-start
slowly ramps the lamp current to reduce the potential to
create audible transformer noise.
There are two methods to control the duty cycle and
frequency of the burst-dimming DPWM. If the PWM_EN
pin is tied low, then the analog-control method is
enabled; a 0V to 3.3V analog voltage at the BRIGHT
input pin determines the duty cycle of a digital pulse-
width modulated (DPWM) signal. The frequency of the
DPWM signal is determined by the value of the resistor
tied from the POSC pin to ground. The slope of the
BRIGHT dimming input is either positive or negative
based on whether the SLOPE pin is tied low or high,
respectively.
DS3991
Low-Cost CCFL Controller
_______________________________________________________________________________________ 9
If the PWM_EN pin is tied high, the digital control
method is enabled and an external PWM signal
between 80Hz and 300Hz is applied at the POSC/PWM
pin to set the brightness of the lamp. In the digital con-
trol method, the SLOPE and BRIGHT pins are not used.
Lamp Strike
On lamp strike, the DS3991 boosts the normal operating
lamp frequency by 33%. This is done to increase the
voltage created and help ensure that the lamp strikes.
Once the controller detects that the lamp has struck, the
frequency is returned to the normal lamp frequency.
Setting the Lamp and DPWM Frequencies Using
External Resistors
Both the lamp and DPWM frequencies are set using
external resistors. The resistance required for either fre-
quency can be determined using the following formula:
where K = 4000kΩ x kHz for lamp frequency calcula-
tions, K = 4kΩ x kHz for DPWM frequency calculations.
Example: Select the resistor values to configure the
DS3991 to have a 50kHz lamp frequency and a 160Hz
DPWM frequency. For the DPWM resistor calculation, K
= 4kΩ x kHz. For the lamp frequency resistor (R
LOSC
)
calculation, K = 4000kΩ x kHz. The formula above can
now be used to calculate the resistor values for R
LOSC
and R
POSC
as follows:
Supply Monitoring
The DS3991 has supply-voltage monitors (SVML and
SVMH) for the inverter’s DC supply (V
INV
) and an
undervoltage lockout for the V
CC
supply to ensure that
voltage levels are adequate for proper operation. The
inverter supply is monitored for overvoltage conditions
at the SVMH pin and undervoltage conditions at the
SVML pin. External resistor-dividers at each SVM input
feed into two comparators, both having 2V thresholds
(see Figure 2). Using the equation below to determine
the resistor values, the SVMH and SVML trip points
(V
TRIP
) can be customized to shut off the inverter when
the inverter supply voltage rises above or drops below
specified values.
Operating with the inverter supply at too low of a level can
prevent the transformer from reaching the strike voltage
and could potentially cause numerous other problems.
Operating with the inverter voltage at too high of a level
can be damaging to the inverter components. Proper use
of the SVMs can prevent these problems. If desired, the
high and/or low SVMs can be disabled by connecting the
SVMH pin to GND and the SVML pin to VCC.
The SVMH and SVML are high-impedance inputs and
noise on the inverter supply can cause the monitors to
inadvertently trigger even though the inputs contain hys-
teresis. The user may wish to add a lowpass filter to
reduce the noise present at the SVMH and SVML inputs.
The V
CC
monitor is a 5V supply undervoltage lockout
(UVLO) that prevents operation when the DS3991 does
not have adequate voltage for its analog circuitry to
operate or to drive the external MOSFETs. The V
CC
monitor features hysteresis to prevent V
CC
noise from
V
TRIP
= 2.0
R
1
+ R
2
R
1
R
POSC
=
4kkHz
0.160kHz
= 25k
R
LOSC
=
4000kkHz
50kHz
= 80k
R
OSC
=
K
f
OSC
80Hz TO 300Hz
LAMP CURRENT
SOFT-START
BURST-DIMMING PWM SIGNAL
(EITHER CREATED INSIDE THE DS3991 OR
SOURCED AT THE POSC/PWM PIN)
Figure 1. Digital PWM Dimming and Soft-Start

DS3991Z+HB

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Display Drivers & Controllers CCFL Controller
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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