6V49205APAGI8 Datasheet 6V49205APAG, 6V49205APAGI, 6V49205APAGI8 | P10-P12

IDT6V49205A

FREESCALE P10XX AND P20XX SYSTEM CLOCK W/66.66M DDR CLOCK

IDT®

FREESCALE P10XX AND P20XX SYSTEM CLOCK W/66.66M DDR CLOCK 10

IDT6V49205A REV Q 112316

Byte 0 Frequency and Spread Select Register

Bit Name Description Type Default

7 SS4 RW 0

6 SS3 RW 0

5 SS2 RW 0

4 SS1 RW 0

3 SS0 RW 0

2 REF_5_EN Output enable for REF_5 RW 1

1 REF_4_EN Output enable for REF_4 RW 1

0 REF_3_EN Output enable for REF_5 RW 1

Byte 1 Output Enable Register

Bit Name Description Type Default

7 REF_2_EN Output enable for REF_2 RW 1

6 REF_1_EN Output enable for REF_1 RW 1

5 REF_0_EN Output enable for REF_0 RW 1

4 USB_CLK1_EN Output enable for USB_CLK1 RW 1

3 USB_CLK2_EN Output enable for USB_CLK2 RW 1

2 CK2.048_0_EN Output enable for CK2.048_0 RW 1

1 CK2.048_1_EN Output enable for CK2.048_1 RW 1

0 DDRCLK_EN Output enable for DDRCLK RW 1

Byte 2 Output Enable Register

Bit Name Description Type Default

7 Sys_CCB_EN Output enable for Sys_CCB RW 1

6 PCIe5_EN Output enable for PCIe5 RW 1

5 PCIe4_EN Output enable for PCIe4 RW 1

4 PCIe3_EN Output enable for PCIe3 RW 1

3 PCIe2_EN Output enable for PCIe2 RW 1

2 PCIe1_EN Output enable for PCIe1 RW 1

1 PCIe0_EN Output enable for PCIe0 RW 1

0 125M_EN Output enable for 125M RW 1

Byte 3 Slew Rate Control Register

Bit Name Description Type Default

7 USB1_SLEW1 RW 0

6 USB1_SLEW0 RW 1

5 USB2_SLEW1 RW 0

4 USB2_SLEW0 RW 1

3 CK2.048_SLEW1 RW 1

2 CK2.048_SLEW0 RW 1

1 Sys_CCB_SLEW1 RW 0

0 Sys_CCB_SLEW0 RW 1

Byte 4 Slew Rate Control Register

Bit Name Description Type Default

7 66M_Slew1 RW 0

6 66M_Slew0 RW 1

5 0

4 1

3FS1 RW Latch

2FS0 RW Latch

1 USB1_fSel USB_CLK1 Clock Frequency Select RW 0

0 USB2_fSel USB_CLK2 Clock Frequency Select RW 1

Byte 5 is Reserved

PCIE Spread Selection Table See Table 1: PCIE Spread Table

Output Disabled Output Enabled

CK2.048_0 and CK2.048_1 Slew Rate

Control

See CK2.048 Electrical Tables

Sys_CCB Slew Rate Control See Sys_CCB Electrical Tables

USB_CLK1 Slew Rate Control See USB Electrical Tables

USB_CLK2 Slew Rate Control See USB Electrical Tables

66MCLK Slew Rate Control See 66M Electrical Tables

Sys_CCB Frequency Select Latch

See Table 3: Sys_CCB Frequency

Selection

12MHz 24MHz

Reserved

Sys_CCB and DDRCLK Spread

Selection Table

See Table 2: Sys_CCB and DDRCLK

Spread Table

IDT6V49205A

FREESCALE P10XX AND P20XX SYSTEM CLOCK W/66.66M DDR CLOCK

IDT®

FREESCALE P10XX AND P20XX SYSTEM CLOCK W/66.66M DDR CLOCK 11

IDT6V49205A

REV Q 112316

Recommended Crystal Characteristics

Byte 6 PCI Express Amplitude Control Register

Bit Name Description Type Default

7 PCIE_AMP1 RW 0

6 PCIE_AMP0 RW 1

5 Reserved Reserved R 1

4 SELPCIE125#_100 PCI Express latch select R latch

3 Reserved Reserved RW 0

2 Reserved Reserved RW 1

1 Reserved Reserved RW 0

0 Reserved Reserved RW 1

Byte 7 Revision and Vendor ID Register

Bit Name Description Type Default

7REV ID R 0

6REV ID R 0

5REV ID R 0

4REV ID R 0

3 Vendor ID R 0

2 Vendor ID R 0

1 Vendor ID R 0

0 Vendor ID R 1

Byte 8 Byte Count Register

Bit Name Description Type Default

7BC7 RW 0

6BC6 RW 0

5BC5 RW 0

4BC4 RW 0

3BC3 RW 0

2BC2 RW 1

1BC1 RW 0

0BC0 RW 1

Revision ID

Vendor ID

PCI Express Amplitude Control

See Table 4 PCIe Amplitude Selection

Table

125MHz 100MHz

Writing to this register will configure how

many bytes will be read back.

Byte Count Programming b(7:0)

PARAMETER VALUE UNITS NOTES

Frequency 25 MHz 1

Resonance Mode Fundamental

Frequency Tolerance @ 25°C

20 PPM Max 1

Frequency Stability, ref @ 25°C Over

Operating Temperature Range

20 PPM Max 1

Temperature Range (commerical) 0~70 °

Temperature Range (industrial) -40~85 °

Equivalent Series Resistance (ESR) 50

Ω

Max 1

Shunt Capacitance (C

)7pF Max1

Load Capacitance (C

)8pF Max1

Drive Level 0.3 mW Max 1

Aging per year ±5 PPM Max 1

IDT6V49205A

FREESCALE P10XX AND P20XX SYSTEM CLOCK W/66.66M DDR CLOCK

IDT®

FREESCALE P10XX AND P20XX SYSTEM CLOCK W/66.66M DDR CLOCK 12

IDT6V49205A REV Q 112316

Test Loads

Thermal Characteristics (48-TSSOP) PAG48

Marking Diagrams

Notes:

1. ‘$’ is the mark code.

2. YYWW is the last two digits of the year, and the week number that the part was assembled.

3. “G” after the two-letter package code denotes Pb free package.

4. “I” denotes industrial temperature range.

5. Bottom marking: country of origin if not USA.

2pF

L inches

Differential Zo

2pF

Low-Power push-pull HCSL Output test load

(standard PCIe test load)

Rs=39

Test Load

CL=4.7pF

except

66M_SS

outputs

where

CL=15pf

Single-ended

Output

Device

Differential Test Load, Zo = 100ohm, L = 5 inches

PARAMETER SYMBOL CONDITIONS PKG

TYP

VALUE

UNITS NOTES

Junction to Case 28 °

C/W

Junction to Base 42 °

C/W

JA0

Junction to Air, still air 62 °

C/W

JA1

Junction to Air, 1 m/s air flow 54 °

C/W

JA3

Junction to Air, 3 m/s air flow 51 °

C/W

PAG48Thermal Resistance

IDT

6V49205APAGI

YYWW$

48TSSOP

IDT

6V49205APAG

YYWW$

48TSSOP

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15

6V49205APAGI8

Mfr. #:

Buy 6V49205APAGI8

Manufacturer:

IDT

Description:

Clock Generators & Support Products QorIQ Clock Synthesi

Lifecycle:

New from this manufacturer.

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6V49205APAGI8

6V49205APAGI8

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