6V49205APAGI8 Datasheet 6V49205APAG, 6V49205APAGI, 6V49205APAGI8 | P4-P6

IDT6V49205A

FREESCALE P10XX AND P20XX SYSTEM CLOCK W/66.66M DDR CLOCK

IDT®

FREESCALE P10XX AND P20XX SYSTEM CLOCK W/66.66M DDR CLOCK 4

IDT6V49205A REV Q 112316

Table 1: PCIEX Spread Table (selectable via SMBUS)

Table 2: Sys_CCB and DDR Spread Table (selectable via SMBUS)

Table 3: Sys_CCB Frequency Select Table (Latched and selectable via SMBUS)

Table 4: PCI Express Amplitude Control

FS1 /

B4b3

FS0 /

B4b2

Sys_CCB (MHz)

00 66.66

0 0 100

01 80

01 83.33

SELPCIE125#_100

B6b4

B0b4 B0b3 Spread %

0 (125MHz) x x No Spread

1 (100MHz) 0 0 No Spread (default)

1 (100MHz) 0 1 Down -0.5%

1 (100MHz) 1 0 Down -0.75%

1 (100MHz) 1 1 No Spread

*Once in spread mode, do not return to non spread without reset

B0b7 B0b6 B0b5 S

read %

0 0 0 No Spread (default)

0 0 1 Down -0.5%

0 1 0 Down -0.75%

0 1 1 Down -0.25%

100 Reserved

101 Reserved

110 Reserved

111 Reserved

B6b7 B6b6 PCIe Amplitude

0 0 700mV

0 1 800mV

1 0 900mV

1 1 1000mV

IDT6V49205A

FREESCALE P10XX AND P20XX SYSTEM CLOCK W/66.66M DDR CLOCK

IDT®

FREESCALE P10XX AND P20XX SYSTEM CLOCK W/66.66M DDR CLOCK 5

IDT6V49205A

REV Q 112316

Absolute Maximum Ratings

Stresses above the ratings listed below can cause permanent damage to the IDT6V49205A. These ratings, which are

standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any

other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute

maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over

the recommended operating temperature range.

Electrical Characteristics - Input/Supply/Common Output DC Parameters

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Notes

Maximum Supply Voltage VDDxxx Supply Voltage 4.6 V 1

Maximum Input Voltage V

Referenced to GND VDD + 0.5 V 1

Minimum Input Voltage V

Referenced to GND GND - 0.5 V 1

Storage Temperature Ts - -65 150

JunctionTemperature Tj - 125 °C 1

Input ESD protection ESD prot Human Body Model 2000 V 1

Operation under these conditions is neither implied, nor guaranteed.

NOTES on Absolute Max Parameters

AMB

= -40 to +85°C; V

= 3.3 V +/-5%, All outputs driving test loads (unless noted otherwise).

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Notes

Ambient Operating Temp T

AMB

- -40 25 85 °C

Supply Voltage VDDxxx Supply Voltage 3.135 3.3 3.465 V

Power supply Ramp Time T

PWRRMP

Power supply ramp must be montonic 4 ms

Latched Input High Voltage V

IH_LI

Single-ended Latched Inputs 2.1 V

+ 0.3 V

Latched Input Low Voltage V

IL_LI

Single-ended Latched Inputs V

- 0.3 0.8 V

Input Leakage Current I

= V

DD ,

GND -5 5 uA 2

Operating Supply Current I

DDOP3.3

All outputs loaded and running

119

155 mA

Input Frequency F

23 25 27 MHz 3

Pin Inductance L

57 nH

Logic Inputs 1.5 3 5 pF

OUT

Output pin capacitance 5 6 pF

INX

X1 & X2 pins 5 6 pF

Clk Stabilization T

STAB

From VDD Power-Up or de-assertion of PD

to 1st clock

3.2 5 ms

Tfall_SE T

FALL

10 ns 1

Trise_SE T

RISE

10 ns 1

SMBus Voltage V

2.7 3.3 V

Low-level Output Voltage V

OLSMB

@ I

PULLUP

0.4 V

Current sinking at

OLSMB

= 0.4 V

PULLUP

SMB Data Pin 4 mA

SCLK/SDATA

Clock/Data Rise Time

RI2C

(Max VIL - 0.15) to

(Min VIH + 0.15)

1000 ns

SCLK/SDATA

Clock/Data Fall Time

FI2C

(Min VIH + 0.15) to

(Max VIL - 0.15)

300 ns

Maximum SMBus Operating

Frequency

SMBUS

100 kHz

Signal is required to be monotonic in this region.

Input leakage current does not include inputs with pull-up or pull-down resistors

Input Capacitance

Fall/rise time of all 3.3V control inputs from

20-80%

NOTES on DC Parameters: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production).

For margining purposes only. Normal operation should have Fin =25MHz

IDT6V49205A

FREESCALE P10XX AND P20XX SYSTEM CLOCK W/66.66M DDR CLOCK

IDT®

FREESCALE P10XX AND P20XX SYSTEM CLOCK W/66.66M DDR CLOCK 6

IDT6V49205A REV Q 112316

AC Electrical Characteristics - Low Power HCSL-Compatible PCIe Outputs

Electrical Characteristics - Phase Jitter, PCIe Outputs at 100MHz

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES

MHz 2,3

ppm

SSof f

PCIe 100MHz or 125MHz ppm 1,2

ppm

SSon

PCIe @ -0.5% spread, 100MHz only ppm 1,2

Rising/Falling Edge Slew Rate t

SLEW

Differential Measurement 2.2 4.1 5.7 V/ns 1,3,6

Slew Rate Variation t

SLVAR

Single-ended Measurement 1 20 % 1,6

Maximum Output Voltage V

HIGH

Includes overshoot 793 1150 mV 6,7

Minimum Output Voltage V

LOW

Includes undershoot -300 -22 mV 6,7

Differential Voltage Swing V

SWING

Differential Measurement 300 mV 1,6

Crossing Point Voltage V

XABS

Single-ended Measurement 300 419 550 mV 1,4,6

Crossing Point Variation V

XABSVAR

Single-ended Measurement 115 140 mV 1,4,5

Duty Cycle D

CYC

Differential Measurement 45 50.1 55 % 1

PCIe Jitter - Cycle to Cycle PCIe

JC2C

Differential Measurement 36 125 ps 1

PCIe[5:0] Skew T

SKEwPCIe50

Differential Measurement 1172 1500 ps 1,6,8

Spread Spectrum Modulation

Frequency

SSMOD

Triangular Modulation 30 31.5 33 kHz

Notes for PCIe Clocks:

Guaranteed by design and characterization, not 100% tested in production.

Clock Frequency specifications are guaranteed assuming that REF is at 25MHz

Slew rate measured through V_swing voltage range centered about differential zero

Vcross is defined at the voltage where Clock = Clock#.

Only applies to the differential rising edge (Clock rising, Clock# falling.)

At default SMBus settings.

The Freescale P-series CPU's have internal terminations on their SerDes Reference Clock inputs. The resulting amplitude at these inputs will be 1/2 of the

values listed, which are well within the 800mV Freescale specification for these inputs.

This value includes an intentional output-to-output skew of approximately 250ps.

Synthesis error

+/-100

Clock Frequency f Spread off

100.00

125.00

PARAMETER SYMBOL CONDITIONS MIN

TYP

MAX

INDUSTRY

SPEC LIMIT

UNITS

NOTES

hPCIe1

PCIe Gen 1 phase jitter 35 56 86 ps 1,2,3

jphPCIe2Lo

PCIe Gen 2 phase jitter

Lo-band content

1.6 2.4 3

(RMS)

1,2,3

jphPCIe2Hi

PCIe Gen 2 phase jitter

Hi-band content

1.9 2.8 3.1

(RMS)

1,2,3

jphPCIe3

PCIe Gen 3 phase jitter 0.5 0.83 1

(RMS)

1,2,3

Notes on Phase Jitter:

Sample size of at least 100K cycles. This fi

ures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1

-12

Applies to PCIe outputs @ default amplitude and 100MHz with spread off or at -0.5%.

See http://www.pcisi

.com for complete specs. Guaranteed by desi

n and characterization, not tested in production.

Jitter, Phase

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15

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