IDT6V49205A
FREESCALE P10XX AND P20XX SYSTEM CLOCK W/66.66M DDR CLOCK
IDT®
FREESCALE P10XX AND P20XX SYSTEM CLOCK W/66.66M DDR CLOCK 13
IDT6V49205A
REV Q 112316
Package Outline and Package Dimensions (PAG48, 48-pin TSSOP, 6.10 mm Body, 0.50 Pitch)
Package dimensions are kept current with JEDEC Publication No. 95
Ordering Information
“G” after the two-letter package code denotes Pb-Free configuration, RoHS compliant.
For an NLG I-temp device, see the 6V49205B.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes
no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No
other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications
such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by IDT. IDT does not authorize or warrant any IDT product for use in life support devices or
critical medical instruments.
Part / Order Number Marking Shipping Packaging Package Temperature
6V49205APAGI see page 12 Tubes 48-pin TSSOP -40to +85C
6V49205APAGI8 Tape and Reel 48-pin TSSOP -40to +85C
6V49205APAG see page 12 Tubes 48-pin TSSOP 0to +70C
6V49205APAG8 Tape and Reel 48-pin TSSOP 0to +70C
INDEX
AREA
1 2
48
D
E1
E
SEATING
PLANE
A1
A
A2
e
- C -
b
aaa C
c
L
*For reference only. Controlling dimensions in mm.
Millimeters Inches*
Symbol Min Max Min Max
A--1.20--0.047
A1 0.05 0.15 0.002 0.006
A2 0.80 1.05 0.032 0.041
b 0.17 0.27 0.007 0.011
c 0.09 0.20 0.0035 0.008
D 12.40 12.60 0.488 0.496
E 8.10 BASIC 0.319 BASIC
E1 6.00 6.20 0.236 0.244
e 0.50 Basic 0.020 Basic
L 0.45 0.75 0.018 0.030
0 8 0 8
aaa -- 0.10 -- 0.004
IDT6V49205A
FREESCALE P10XX AND P20XX SYSTEM CLOCK W/66.66M DDR CLOCK
IDT®
FREESCALE P10XX AND P20XX SYSTEM CLOCK W/66.66M DDR CLOCK 14
IDT6V49205A REV Q 112316
Revision History
Rev. Issue Date Issuer Description Page #
L 12/12/2013 R. Wade
1. Extensive overhaul of Electrical tables to more closely align
with Freescale published specifications.
2. Updated electrical tables with characterization data.
3. Clarified SMBus registers for Slew Rate Controls
4. Moved electrical tables in front of SMBus for consistency
with other data sheets.
5. Updated Thermal Data and added test loads for clarity.
6. Updated front page text
7. Minor updates to pin names (mainly power and ground) for
consistency and clarity
Various
L 1/9/2014 J. Tajnai
Table 2: Sys_CCB and DDR Spread Table; 100~111 marked as
Reserved.
4
M 2/12/2014 D. Christenberry Added 48-pin VFQFPN package, diagrams, and references Various
N 3/24/2015 RDW
Updated ordering information to remove I-temp NLG package,
and to add commercial PAG and NLG packages
14
P
5/11/2016
RDW
1. Correct PCIeT_LRn and PCIeC_LRn to be PCIeT_Ln and
PCIeC_Ln to indicate that the Rs for the PCIe outputs is outside
the part and to correct the pin description accordingly. The test
loads for the device are correct.
2. Update block diagram PCIe pin names to be consistent.
1-3
Q
11/22/2016
RDW
1. Undo Revision P
2. PCIe outputs have integrated terminations for 100ohm
differential Zo.
3. Update Test Loads
4. Update Features/Benefits
1-3, 12
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IDT6V49205A
FREESCALE P10XX AND P20XX SYSTEM CLOCK W/66.66M DDR CLOCK

6V49205APAGI8

Mfr. #:
Manufacturer:
IDT
Description:
Clock Generators & Support Products QorIQ Clock Synthesi
Lifecycle:
New from this manufacturer.
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