2
Functional Description
Receiver Section
Design
The receiver section for the HFCT-5914ATLZ contains
an InGaAs/InP photo detector and a pre-amplifier
mounted in an optical subassembly. This optical subas-
sembly is coupled to a post-amplier/decision circuit
on a circuit board. The design of the optical assembly is
such that it provides better than 12 dB Optical Return
Loss (ORL).
The post-amplier is ac coupled to the pre-amplier
as illustrated in Figure 1. The coupling capacitors are
capable of passing the Gigabit Ethernet test pattern at
1.25 Gb/s without any signicant distortion or perfor-
mance penalty. If a lower signal rate, or a code which
has signicantly more low frequency content is used,
sensitivity, jitter and pulse distortion could be degrad-
ed.
Figure 1 also shows a lter function which limits the
bandwidth of the pre-amplier output signal. The lter
is designed to bandlimit the pre-amplier output noise
and thus improve the receiver sensitivity.
These components will reduce the sensitivity of the re-
ceiver as the signal bit rate is increased above 1.25 Gb/s.
The device incorporates a photodetector bias circuit.
This output must be connected to V
CC
and can be moni-
tored by connecting through a series resistor (see Ap-
plication Section).
Noise Immunity
The receiver includes internal circuit components to
lter power supply noise. However under some condi-
tions of EMI and power supply noise, external power
supply ltering may be necessary (see Application Sec-
tion).
The Signal Detect Circuit
The signal detect circuit works by sensing the peak level
of the received signal and comparing this level to a ref-
erence. The SD output is low voltage TTL.
Figure 1. Receiver Block Diagram
TRANS-
IMPEDANCE
PRE-
AMPLIFIER
FILTER
GND
AMPLIFIER
PECL
OUTPUT
BUFFER
TTL
OUTPUT
BUFFER
DATA OUT
SIGNAL
DETECT
CIRCUIT
SD
DATA OUT
PHOTODETECTOR
BIAS
