6
Pin Descriptions:
Pin 1 Photo Detector Bias, VpdR:
This pin enables monitoring of photo detector bias current.
The pin should either be connected directly to V
CC
RX, or to
V
CC
RX through a resistor (max 200 W) for monitoring
photo detector bias current.
Pins 2, 3, 6 Receiver Signal Ground V
EE
RX:
Directly connect these pins to the receiver ground
plane.
Pins 4, 5 DO NOT CONNECT
Pin 7 Receiver Power Supply V
CC
RX:
Provide +3.3 V dc via the recommended dc receiver power
supply lter circuit. Locate the power supply lter circuit as
close as possible to the V
CC
RX pin. Note: the lter circuit
should not cause V
CC
to drop below minimum specica-
tion.
Pin 8 Signal Detect SD:
Normal optical input levels to the receiver result in a
logic “1” output.
Low optical input levels to the receiver result in a logic
“0” output.
This Signal Detect output can be used to drive a LVTTL
input on an upstream circuit, such as Signal Detect in-
put or Loss of Signal-bar.
Connection Diagram
Figure 5. Pin Out Diagram (Top View)
LASER DIODE OPTICAL POWER MONITOR - POSITIVE END
LASER DIODE OPTICAL POWER MONITOR - NEGATIVE END
LASER DIODE BIAS CURRENT MONITOR - POSITIVE END
LASER DIODE BIAS CURRENT MONITOR - NEGATIVE END
TRANSMITTER SIGNAL GROUND
TRANSMITTER DATA IN BAR
TRANSMITTER DATA IN
TRANSMITTER DISABLE
TRANSMITTER SIGNAL GROUND
TRANSMITTER POWER SUPPLY
RX TX
o
o
o
o
o
o
o
o
o
o
1
2
3
4
5
6
7
8
9
10
o
o
o
o
o
o
o
o
o
o
20
19
18
17
16
15
14
13
12
11
PHOTO DETECTOR BIAS
RECEIVER SIGNAL GROUND
RECEIVER SIGNAL GROUND
NOT CONNECTED
NOT CONNECTED
RECEIVER SIGNAL GROUND
RECEIVER POWER SUPPLY
SIGNAL DETECT
RECEIVER DATA OUTPUT BAR
RECEIVER DATA OUTPUT
Top
View
Mounting Studs/
Solder Posts
Package
Grounding Tabs
Pin 9 Receiver Data Out Bar RD-:
PECL logic family. Output internally biased and ac
coupled.
Pin 10 Receiver Data Out RD+:
PECL logic family. Output internally biased and ac
coupled.
Pin 11 Transmitter Power Supply V
CC
TX:
Provide +3.3 V dc via the recommen ded dc transmitter
power supply lter circuit. Locate the power supply l-
ter circuit as close as possible to the VCC TX pin.
Pins 12, 16 Transmitter Signal Ground V
EE
TX:
Directly connect these pins to the transmitter signal
ground plane.
Pin 13 Transmitter Disable T
DIS
:
Optional feature, connect this pin to +3.3 V TTL logic
high “1” to disable module. To enable module connect
to TTL logic low “0”.
Pin 14 Transmitter Data In TD+:
PECL logic family. Internal terminations are provided (Ter-
minations, ac coupling).
Pin 15 Transmitter Data In Bar TD-:
Internal terminations are provided (Terminations, ac
coupling).
