10
LTC3445
3445fa
FU CTIO AL DIAGRA S
U
U
W
Figure 2. Buck Regulator Detail
V
FB
V
REF
EA
PEAK CURRENT LEVEL REFERENCE
BURST
R
S
SW
PFET
NFET
3445 F02
L
L
V
CC1
I
COMP
I
RCOMP
QB
Q
R
S
LOGIC
OSC
11
LTC3445
3445fa
TI I G DIAGRA
UWW
t
BUF
t
SUSTO
3445 TD
t
HD(STA)
t
HD(DAT)
t
SU(STA)
t
SU(DAT)
t
LOW
t
HIGH
t
r
t
f
t
HD(STA)
SCL
SDA
START
CONDITION
REPEATED START
CONDITION
STOP
CONDITION
START
CONDITION
I
2
C Fast Mode Timing Specifications (for Reference)
SYMBOL PARAMETER MIN TYP MAX UNITS
f
I2C(MAX)
Maximum I
2
C Operating Frequency 0 400 kHz
t
BUF
Bus Free Time Between Stop and Start Condition 1.3 µs
t
HD(RSTA)
Hold Time After (Repeated) Start Condition 0.6 µs
t
SU(RSTA)
Repeated Start Condition Setup Time 0.6 µs
t
SU(STOP)
Stop Condition Setup Time 0.6 µs
t
HD(DAT)
Data Hold Time 0 0.9 ns
t
SU(DAT)
Data Setup Time 100 ns
t
LOW
Clock Low Period 1.3 µs
t
HIGH
Clock High Period 0.6 µs
t
SP
Pulse Width of Spikes Suppressed by Input Filter 0 50 ns
t
f
Clock, Data Fall Time (Note 1) 20 + 0.1 300 ns
• C
B
tr Clock, Data Rise Time (Note 1) 20 + 0.1 300 ns
• C
B
Note 1: C
B
= Capacitance of one bus line.
OPERATIO
U
(refer to Figure 1)
BUCK REGULATOR
Main Control Loop
The LTC3445 uses a constant or spread spectrum fre-
quency, current mode step-down architecture (Figure 2).
Both the main (P-channel MOSFET) and synchronous
(N-channel MOSFET) switches are internal. During normal
operation, the internal top power MOSFET is turned on
each cycle when the oscillator sets the RS latch, and
turned off when the current comparator, I
COMP
, resets the
RS latch. The peak inductor current at which I
COMP
resets
the RS latch is controlled by the output of error amplifier
EA. When the load current increases, it causes a slight
decrease in the feedback voltage, FB, relative to an internal
reference voltage, which in turn, causes the EA’s output
voltage to increase until the average inductor current
matches the new load current. While the top MOSFET is
off, the bottom MOSFET is turned on until either the
inductor current starts to reverse, as indicated by the
current reversal comparator I
RCMP
, or the beginning of the
next clock cycle.
12
LTC3445
3445fa
OPERATIO
U
Burst Mode Operation
The LTC3445 is capable of Burst Mode operation, in which
the internal power MOSFETs operate intermittently based
on load demand.
In Burst Mode operation, the peak current of the inductor
is set to approximately 200mA regardless of the output load.
Each burst event can last from a few cycles at light loads
to almost continuous cycling with short sleep intervals at
moderate loads. In between these burst events, the power
MOSFETs and any nonessential circuitry are turned off, re-
ducing the buck regulator’s quiescent current to 6µA. In this
sleep state, the load current is being supplied solely from
the output capacitor. As the output voltage droops, the EA’s
output rises above the sleep threshold, signaling the BURST
comparator to trip and turn the top MOSFET on. This pro-
cess repeats at a rate that is dependent on the load demand.
Short-Circuit Protection
When the output is shorted to ground, the frequency of the
oscillator is reduced to about 300kHz. This frequency
foldback ensures that the inductor current has more time
to decay, thereby preventing current runaway. The
oscillator’s frequency will progressively increase to 1.5MHz
when V
OUT
rises above 0V.
Low Supply Operation
The LTC3445 will operate with input supply voltages as
low as 2.5V, but the maximum allowable output current is
reduced at this low voltage. Figure 3 shows the reduction
in the typical maximum output current as a function of
input voltage for various output voltages.
Slope Compensation and Inductor Peak Current
Slope compensation provides stability in constant fre-
quency architectures by preventing subharmonic oscilla-
tions at high duty cycles. It is accomplished internally by
adding a compensating ramp to the inductor current sig-
nal at duty cycles in excess of 40%. Normally, this results
in a reduction of maximum inductor peak current for duty
cycles >40%. However, the LTC3445 uses a patent-pend-
ing scheme that counteracts this compensating ramp,
which allows the maximum inductor peak current to re-
main unaffected throughout all duty cycles.
(refer to Figure 1)
V
CC1
(V)
2.5
400
MAXIMUM LOAD CURRENT (mA)
600
800
1000
3.5
4.53
4
5
3445 F03
1200
1400
500
700
900
1100
1300
5.5
DAC (MIN)
DAC (MAX)
Figure 3. Buck Maximum Peak Current vs V
CC1
Spread Spectrum
The LTC3445 has a spread spectrum mode that can be
enabled via two register bits. In the spread spectrum
mode, the switching frequency is dithered about a center
frequency of 1.5MHz. Spread spectrum lowers noise at the
regulated output and at the input.
Figure 4 shows the noise reduction capabilities of the
LTC3445 in spread spectrum mode. The percent spread of
the frequency is controlled by two bits in register 5.
00 = 0% Spread
01 = 7.4% Spread
10 = 14.8% Spread
11 = 22.4% Spread
DAC
The buck output voltage is controlled by programming a
6-bit DAC register (REG0[5:0]) and GO bit (REG2[0]). The
output voltage range is 0.85V to 1.55V in ~15mV steps.
The DAC setting range is from 0 to 48. Any settings above
48 will default to the 48 settings value. When the desired
DAC setting is loaded, the GO bit needs to be changed from
0 to 1. Once the GO bit transition occurs, V
OUT
will begin
to change to the DAC setting loaded at that instant.
Slew Rate
A 2-bit register is used to control the rate of change of
V
OUT
between DAC settings. The slew rate is controlled
by stepping V
OUT
to its new setting using a series of

LTC3445EUF#TRPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Controllable Buck Regulator w/ Two LDOs in QFN
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet