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LTC3445EUF#TRPBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24
19
LTC3445
3445fa
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V
OUT
immediately shifts by an amount
equal to (∆I
LOAD
• ESR), where ESR is the effective series
resistance of C
OUT
. ∆I
LOAD
also begins to charge or
discharge C
OUT
, which generates a feedback error signal.
The regulator loop then acts to return V
OUT
to its steady-
state value. During this recovery time V
OUT
can be moni-
tored for overshoot or ringing that would indicate a stability
problem. For a detailed explanation of switching control
loop theory, see Application Note 76.
A second, more severe transient is caused by switching in
loads with large (>1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with C
OUT
, causing a rapid drop in V
OUT
. No regulator can
deliver enough current to prevent this problem if the load
switch resistance is low and it is driven quickly. The only
solution is to limit the rise time of the switch drive so that
the load rise time is limited to approximately (25 • C
LOAD
).
Thus, a 10µF capacitor charging to 3.3V would require a
250µs rise time, limiting the charging current to about
130mA.
LDO REGULATORS
The LDOs in the LTC3445 are 50mA low dropout regula-
tors with low quiescent and shutdown currents. Each
device is capable of supplying 50mA at a dropout voltage
of 300mV. The LDOs are current limited to greater than
50mA but less than 75mA. The output voltages of the
LDOs are set with external resistive dividers according to
the following formula:
V
LDOOUT1
= 0.6(1 + R1/R2) (4)
V
LDOOUT2
= 0.6(1 + R3/R4) (5)
Output Capacitance and Transient Response
The LTC3445 LDOs are designed to be stable with a wide
range of output capacitors. A minimum output capacitor
of 2.2µF with an ESR of 3Ω or less is recommended to
internal power MOSFET switches. Each time the gate is
switched from high to low to high again, a packet of
charge, dQ, moves from V
CC1
to ground. The resulting
dQ/dt is the current out of V
CC1
that is typically larger
than the DC bias current. In continuous mode, I
GATECHG
= f(Q
T
+ Q
B
) where Q
T
and Q
B
are the gate charges of the
internal top and bottom switches. Both the DC bias and
gate charge losses are proportional to V
CC1
and thus
their effects will be more pronounced at higher supply
voltages.
2. I
2
R losses are calculated from the resistances of the
internal switches, R
SW
, and external inductor R
L
. In
continuous mode, the average output current flowing
through inductor L is “chopped” between the main
switch and the synchronous switch. Thus, the series
resistance looking into the SW pin is a function of both
top and bottom MOSFET R
DS(ON)
and the duty cycle
(DC) as follows:
R
SW
= (R
DS(ON)TOP
)(DC) + (R
DS(ON)BOT
)(1 – DC)
The R
DS(ON)
for both the top and bottom MOSFETs can
be obtained from the Typical Performance Charateristics
curves. Thus, to obtain I
2
R losses, simply add R
SW
to
R
L
and multiply the result by the square of the average
output current.
Other losses including C
IN
and C
OUT
ESR dissipative
losses and inductor core losses generally account for
less than 2% total additional loss.
APPLICATIO S I FOR ATIO
WUUU
Figure 8. Power Loss vs Load Current, V
CC1
= 3.6V
LOAD CURRENT (mA)
1
POWER LOSS (mW)
10
100
1000
0.1 10 100 1000
3445 F08
0.1
1
DAC MIN
DAC MAX
20
LTC3445
3445fa
prevent oscillations. The LTC3445 LDOs are micropower
devices and output transient response will be a function of
output capacitance. Larger values of output capacitance
decrease the peak deviations and provide improved tran-
sient response for larger load current changes.
PowerPath CONTROLLER
The PowerPath circuitry in the LTC3445 is used to provide
backup power from V
BACKUP
to the V
CC
BATT pin when
V
CC1
is low or disconnected. When V
CC1
is below 2.8V, the
PowerPath routes V
BACKUP
, typically a coin cell, to the V
CC
BATT pin. While V
BACKUP
is selected there is no current
limiting except for a small (<5Ω) resistance from the
V
BACKUP
input to the V
CC
BATT output. The LTC3445 sinks
less than 6.5µA from V
BACKUP
when it is selected and sinks
less than 0.1µA from V
BACKUP
when it is not selected.
When V
CC1
exceeds 2.8V, V
BACKUP
is disconnected from
V
CC
BATT and an internal LDO regulates the V
CC
BATT
voltage to the minimum of V
CC1
or typically 3V. The
internal LDO is current limited to less than 50mA, but
greater than 10mA. Capacitance on the V
CC
BATT pin
should be at least 2µF with an ESR less than 3Ω.
V
BACKUP
will be routed to the V
CC
BATT output when the
main battery voltage falls below 2.4V. As the main battery,
V
CC1
, voltage drops from 3V to 2.4V, the LDO will be in
dropout, V
CC
BATT will follow V
CC1
down, rebounding to
V
BACKUP
when V
CC1
falls below 2.4V. If V
CC1
is removed
quickly, the capacitor on V
CC
BATT will limit the V
CC
BATT
droop until V
BACKUP
is switched in.
The V
TRACK
input offers the capability of the V
CC
BATT
voltage to follow the voltage on V
TRACK
up to V
CC1
. In
effect, V
TRACK
overrides the internal reference of the LDO,
resulting in the LDO output (V
CC
BATT) having a gain of 1
relative to V
TRACK
once V
TRACK
exceeds a typical value of
3V. V
CC
BATT will follow V
TRACK
to within 200mV provid-
ing V
TRACK
does not exceed the dropout voltage of the
LDO, which is powered by V
CC1
.
V
BACKUP
should be present prior to V
CC1
being connected.
V
BACKUP
provides power to the BATTFAULT driver which
APPLICATIO S I FOR ATIO
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is used to detect an absent or low V
CC1
. If V
BACKUP
is not
present, the LTC3445 will be unable to pull the BATTFAULT
pin low to signal a V
CC1
fault condition.
Output Capacitance and Transient Response
The LDO used LTC3445 PowerPath is designed to be
stable with a wide range of output capacitors. A minimum
output capacitor of 2.2µF with an ESR of 3Ω or less is
recommended to prevent oscillations. The LTC3445
PowerPath LDO is a micropower device and output tran-
sient response will be a function of output capacitance.
Larger values of output capacitance decrease the peak
deviations and provide improved transient response for
larger load current changes.
THERMAL CONSIDERATIONS
In most applications the LTC3445 does not dissipate
much heat due to its high efficiency. But, in applications
where the LTC3445 is running at high ambient tempera-
ture with low supply voltage and high duty cycles, such as
in dropout, the heat dissipated may exceed the maximum
junction temperature of the part. If the junction tempera-
ture reaches approximately 150°C, both power switches
will be turned off and the SW node will become high
impedance. The remaining regulators will also turn off.
To ensure the LTC3445 doesn’t exceed the maximum
junction temperature, the user will need to do some
thermal analysis. The goal of the thermal analysis is to
determine whether the power dissipated exceeds the
maximum junction temperature of the part. The tempera-
ture rise is given by:
T
R
= θ
JA
• (PD
BUCK
+ PD
LDO1
+ PD
LDO2
+ PD
PowerPath
)
where P
D
is the power dissipated by the regulator and θ
JA
is the thermal resistance from the junction of the die to the
ambient temperature.
The junction temperature, T
J
, is given by:
T
J
= T
A
+ T
R
where T
A
is the ambient temperature.
21
LTC3445
3445fa
As an example, consider the LTC3445 in dropout at an
input voltage of 2.7V, an ambient temperature of 70°C, a
buck load current of 600mA, LDO1 set to 1.3V with a load
of 25mA, LDO2 set to 1.1V with a load of 15mA, and the
PowerPath regulator at 2.5V with a load of 6µA. From the
typical performance graph of switch resistance, the R
DS(ON)
of the P-channel switch at 70°C is approximately 0.52Ω.
Therefore, power dissipated by the part is:
P
D(BUCK)
= I
LOAD
2
• R
DS(ON)
= 180mW
P
D(LDO1)
= (2.7 – 1.3)V • 0.025A = 35mW
P
D(LDO2)
= (2.7 – 1.1)V • 0.015A = 24mW
P
D(PowerPath)
= (2.7 – 2.5)V • 6µA = 1.2µW
P
D(TOTAL)
= 0.239W
For the QFN24 package, the θ
JA
is 37°C/W. Thus, the
junction temperature of the regulator is:
T
J
= 70°C + (0.239)(37) = 78.8°C
which is well below the maximum junction temperature of
125°C. Note that at higher supply voltages, the junction
temperature is lower due to reduced switch resistance
(R
DS(ON)
).
PC BOARD LAYOUT CHECKLIST
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3445. These items are also illustrated graphically in
Figures 9 and 10. Check the following in your layout:
1. The power traces, consisting of the GND trace, the SW
trace, the V
CC1
trace and the V
CC2
trace should be kept
short, direct and wide.
2. Does the FB pin connect directly to the output voltage
reference? Ensure that there is no load current running
from the reference voltage and the FB pin.
3. Does the (+) plate of C
IN1
connect to V
CC1
as closely as
possible? This capacitor provides the AC current to the
internal power MOSFETs.
4. Keep the switching node, SW, away from the sensitive
FB node.
5. Keep the (–) plates of C
IN
and C
OUT
as close as possible.
APPLICATIO S I FOR ATIO
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Figure 9 Figure 10
V
CC1
10
V
CC1
GND OUT
3445 F09
SW
RUN
FB
GND
25
NC
12
GND
11
NC
13
SW
14
RUN
15
NC
16
VIA TO
OUT
VIA TO
FB
FB
17
C
IN
C
OUT
L1
V
CC1
10
3445 f10
GND
25
L1
V
OUT
BOLD LINES INDICATE HIGH CURRENT PATH
V
CC1
C
IN
NC
12
GND
11
NC
13
SW
14
RUN
15
NC
16
FB
17
C
OUT
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LTC3445EUF#TRPBF

Mfr. #:
Buy LTC3445EUF#TRPBF
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Controllable Buck Regulator w/ Two LDOs in QFN
Lifecycle:
New from this manufacturer.
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