LC75843UGA-AH Datasheet LC75843UGA-AH | P28-P30

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28

PWM output waveforms

Control data

PWM output

waveforms

W10 W11 W12 W13 W14 W15 W20 W21 W22 W23 W24 W25 W30 W31 W32 W33 W34 W35

1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 0 0 1 (1)

1 1 1 0 0 0 1 1 1 1 0 0 1 1 1 0 1 0 (2)

1 1 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 0 (3)

Control data PWM output waveform frame frequency fp[Hz]

PF0 PF1 PF2 PF3

Internal oscillator operating mode

(The control data OC is 0,

fosc=300[kHz]typ)

External clock operating mode

(The control data OC is 1,

and EXF is 0, f

CK

1=300[kHz]typ)

0 0 0 0 fosc/1536 f

CK

1/1536

1 0 0 0 fosc/1408 f

CK

1/1408

0 1 0 0 fosc/1280 f

CK

1/1280

1 1 0 0 fosc/1152 f

CK

1/1152

0 0 1 0 fosc/1024 f

CK

1/1024

1 0 1 0 fosc/896 f

CK

1/896

0 1 1 0 fosc/768 f

CK

1/768

1 1 1 0 fosc/640 f

CK

1/640

0 0 0 1 fosc/512 f

CK

1/512

1 0 0 1 fosc/384 f

CK

1/384

0 1 0 1 fosc/256 f

CK

1/256

Note: When is setting (PF0, PF1, PF2, PF3)=(1, 1, 0, 1) and (X, X, 1, 1) the frame frequency is same as

frame frequency at the time of the (PF0, PF1, PF2, PF3)=(1, 0, 1, 0) setting (fosc/896, f

CK

1/896).

X:don’t care

Tp=

1

fp

(56/64)Tp

P1 to P4

V

DD

V

SS

(48/64)Tp

P2 to P4

V

SS

V

DD

(40/64)Tp

P2 to P4

V

SS

V

DD

(1)

(32/64)Tp

P1 to P4

V

DD

V

SS

(32/64)Tp

P2 to P4

V

SS

V

DD

(32/64)Tp

P2 to P4

V

SS

V

DD

(3)

(8/64)Tp (8/64)Tp

P1 to P4

V

DD

V

SS

(16/64)Tp

P2 to P4

V

SS

V

DD

(24/64)Tp

P2 to P4

V

SS

V

DD

(2)

(16/64)Tp

(24/64)Tp

(32/64)Tp

Tp Tp

(56/64)Tp

(48/64)Tp

(40/64)Tp

(PWM output Ch1)

(PWM output Ch2)

(PWM output Ch3)

(PWM output Ch1)

(PWM output Ch2)

(PWM output Ch3)

(PWM output Ch1)

(PWM output Ch2)

(PWM output Ch3)

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Clock output waveforms

Control data

Clock frequency of clock output P1

fc(=1/Tc)[Hz]

PS10 PS11

1 0 Clock output function (fosc/2, f

CK

/2)

0 1 Clock output function (fosc/8, f

CK

/8)

P1

Tc

Tc/2

1

fc

Tc=

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Display Control and the

INH

Since the LSI internal data (1/4 duty : the display data D1 to D100 and the control data, 1/3 duty : the display data D1 to

D78 and the control data, 1/2 duty : the display data D1 to D54 and the control data, 1/1 duty : the display data D1 to

D28 and the control data) is undefined when power is first applied, applications should set the

INH

pin low at the same

time as power is applied to turn off the display (This sets the S1/P1 to S4/P4, S5 to S24, COM4/S25,

COM3/S26,COM2/S27, COM1, and S28 pins to the V

SS

level.) and during this period send serial data from the

controller. The controller should then set the

INH

pin high after the data transfer has completed . This procedure

prevents meaningless display at power on. (See Figure 4, Figure 5, Figure 6, Figure 7.)

(1)1/4 duty

[Figure 4]

(2)1/3 duty

[Figure 5]

Display data and

control data transferred

V

DD

t2

CE

INH

Undefined

Defined

Defined Undefined

Undefined

V

IL

1

tc

V

IL

1

(D1 to D100, DT0, DT1)

t1

Internal

data

W10 to W15, W20 to W25,

W30 to W35, PF0 to PF3,

PS10, PS11 to PS40, PS41,

P0 to P2, FC0 to FC3,

DN, EXF, OC, SC, BU

Internal

data

~

Note : t1>1ms

t2>0

tc … 10s min

Display data and

control data transferred

V

DD

t2

CE

INH

Undefined

Defined

Defined Undefined

Undefined

V

IL

1

tc

V

IL

1

(D1 to D78, DT0, DT1)

t1

Internal

data

W10 to W15, W20 to W25,

W30 to W35, PF0 to PF3,

PS10, PS11 to PS40, PS41,

P0 to P2, FC0 to FC3,

DN, EXF, OC, SC, BU

Internal

data

~

Note : t1>1ms

t2>0

tc … 10s min

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