DS80C310
15 of 22
Note 2:
Address is held in a weak latch until overdriven by external memory.
EXTERNAL CLOCK CHARACTERISTICS
PARAMETER SYMBOL MIN TYP MAX UNITS
Clock High Time t
CHCX
10 ns
Clock Low Time t
CLCX
10 ns
Clock Rise Time t
CLCL
5 ns
Clock Fall Time t
CHCL
5 ns
SERIAL PORT MODE 0 TIMING CHARACTERISTICS
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SM2 = 0, 12 clocks per cycle 12t
CLCL
Serial Port Clock Cycle
Time
t
XLXL
SM2 = 1, 4 clocks per cycle 4t
CLCL
ns
SM2 = 0, 12 clocks per cycle 10t
CLCL
Output Data Setup to
Clock Rising
t
QVXH
SM2 = 1, 4 clocks per cycle 3t
CLCL
ns
SM2 = 0, 12 clocks per cycle 2t
CLCL
Output Data Hold from
Clock Rising
t
XHQX
SM2 = 1, 4 clocks per cycle t
CLCL
ns
SM2 = 0, 12 clocks per cycle t
CLCL
Input Data Hold after
Clock Rising
t
XHDX
SM2 = 1, 4 clocks per cycle t
CLCL
ns
SM2 = 0, 12 clocks per cycle 11t
CLCL
Clock Rising Edge to
Input Data Valid
t
XHDV
SM2 = 1, 4 clocks per cycle 3t
CLCL
ns
DEFINITION OF AC SYMBOLS
In an effort to remain compatible with the original 8051 family, this device specifies the same parameters
as such devices, using the same symbols. For completeness, the following are description of the symbols.
t Time
A Address
C Clock
D Input Data
H Logic Level High
L Logic Level Low
I Instruction
P
PSEN
Q Output Data
R
RD
Signal
V Valid
W
WR
Signal
X No longer a valid logic level
Z Tri-State
