DS80C310
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MEMORY ACCESS
The DS80C310 has 256 bytes of scratchpad RAM, but contains no on-chip ROM. Off-chip memory is
accessed using the multiplexed address/data bus on P0 and the MSB address on P2. Timing diagrams are
provided in the
Absolute Maximum Ratings section. Program memory (ROM) is accessed at a fixed rate
determined by the crystal frequency and the actual instructions. As mentioned above, an instruction cycle
requires 4 clocks. Data memory (RAM) is accessed according to a variable speed MOVX instruction as
described below.
STRETCH MEMORY CYCLE
The DS80C310 allows the application software to adjust the speed of data memory access. The
microcontroller can perform the MOVX in as few as 2 instruction cycles. However, this value can be
stretched as needed so that both fast memory and slow memory or peripherals can be accessed with no
glue logic. Even in high-speed systems, it may not be necessary or desirable to perform data memory
access at full speed. In addition, there are a variety of memory-mapped peripherals such as LCD displays
or UARTs that are not fast.
The stretch MOVX is controlled by the Clock Control Register at SFR location 8Eh as described below.
This allows the user to select a stretch value between 0 and 7. A stretch of 0 results in a 2-machine-cycle
MOVX. A stretch of 7 results in a MOVX of 9 machine cycles. Software can dynamically change this
value depending on the particular memory or peripheral.
On reset, the stretch value defaults to 1, resulting in a 3-cycle MOVX. Therefore, RAM access is not
performed at full speed. This is a convenience to existing designs that may not have fast RAM in place.
When maximum speed is desired, the software should select a stretch value of 0. When using very slow
RAM or peripherals, a larger stretch value can be selected. Note that this affects data memory only and
the only way to slow program memory (ROM) access is to use a slower crystal.
Using a stretch value between 1 and 7 causes the microcontroller to stretch the read/write strobe and all
related timing. This results in a wider read/write strobe allowing more time for memory/peripherals to
respond. The timing of the variable speed MOVX is shown in the
Absolute Maximum Ratings section.
Note that full speed access is not the reset default case. Table 2 shows the resulting strobe widths f
or each
stretch value. The memory stretch is implemented using the Clock Control Special Function Register at
SFR location 8Eh. The stretch value is selected using bits CKCON.2–CKCON.0. In the table, these bits
are referred to as M2 through M0. The first stretch (default) allows the use of common 120ns or 150ns
RAMs without dramatically lengthening the memory access.
