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LTC1410CSW#PBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
10
LTC1410
APPLICATIONS INFORMATION
WUU
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capacitors at the end of conversion. During conversion
the analog inputs draw only a small leakage current. If the
source impedance of the driving circuit is low then the
LTC1410 inputs can be driven directly. As source imped-
ance increases so will acquisition time (see Figure 6). For
minimum acquisition time with high source impedance,
a buffer amplifier should be used. The only requirement
is that the amplifier driving the analog input(s) must
settle after the small current spike before the next conver-
sion starts (settling time must be 100ns for full through-
put rate).
SOURCE RESISTANCE (Ω)
10
ACQUISITION TIME (µs)
1
1410 F06
0.1
0.01
100
1k 10k
100k
10
Figure 6. Acquisition Time vs Source Resistance
Choosing an input amplifier is easy if a few requirements
are taken into consideration. First, choose an amplifier
that has a low output impedance (<100Ω) at the closed-
loop bandwidth frequency. For example, if an amplifier is
used in a gain of +1 and has a closed-loop bandwidth of
50MHz, then the output impedance at 50MHz must be
less than 100Ω. The second requirement is that the
closed-loop bandwidth must be greater than 20MHz to
ensure adequate small-signal settling for full throughput
rate. If slower op amps are used, more settling time can
be provided by increasing the time between conversions.
Suitable devices capable of driving the ADC’s inputs
include the LT
®
1360, LT1220, LT1223, LT1224 and
LT1227 op amps.
The noise and the distortion of the input amplifier must
also be considered since they will add to the LTC1410
noise and distortion. The small-signal bandwidth of the
sample-and-hold circuit is 20MHz. Any noise that is present
at the analog inputs will be summed over this entire
bandwidth. Noisy input circuitry should be filtered prior to
the analog inputs to minimize noise. A simple 1-pole RC
filter is usually sufficient. For example, Figure 7 shows a
1000pF capacitor from +A
IN
to ground and a 100Ω source
resistor will limit the input bandwidth to 1.6MHz. Simple
RC filters work well for AC applications, but they will limit
the transient response. For full speed operation, amplifiers
with fast settling and low noise should be chosen.
1
2
3
4
5
0.1µF
10µF
100Ω
ANALOG
INPUT
1000pF
1410 F07
+A
IN
–A
IN
V
REF
REFCOMP
AGND
LTC1410
Figure 7. RC Input Filter
Internal Reference
The LTC1410 has an on-chip, temperature compensated,
curvature corrected, bandgap reference which is factory
trimmed to 2.500V. It is connected internally to a reference
amplifier and is available at V
REF
(Pin 3). See Figure 8a. A
2k resistor is in series with the output so that it can be
1
2
3
+A
IN
–A
IN
LTC1410
4.06V
0.1µF
10µF
R2
40k
R1
2k
ANALOG
INPUT
2.500V
1410 F08a
REFCOMP
AGND
V
REF
4
5
R3
64k
+
–
BANDGAP
REFERENCE
Figure 8a. LTC1410 Reference Circuit
11
LTC1410
APPLICATIONS INFORMATION
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1
2
3
4
5
0.1µF
10µF
ANALOG
INPUT
1410 F08b
LT1019A-2.5
V
OUT
V
IN
5V
+A
IN
–A
IN
V
REF
REFCOMP
AGND
LTC1410
Figure 8b. Using the LT1019-2.5 as an External Reference
easily overdriven in applications where an external refer-
ence is required. The reference amplifier provides buffer-
ing between the internal reference and the capacitive DAC.
The reference amplifier compensation pin REFCOMP
(Pin 4), must be bypassed with a capacitor to ground. The
reference amplifier is stable with capacitors of 1µF or
greater. For the best noise performance, a 10µF tantalum
in parallel with 0.1µF ceramic is recommended.
The V
REF
pin can be driven with an external reference
(Figure 8b), a DAC or other means to provide input span
adjustment. The V
REF
should be kept in the range of 2.25V
to 2.75V for specified linearity.
Full-Scale and Offset Adjustment
Figure 9 shows the ideal input/output characteristics for
the LTC1410. The code transitions occur midway between
successive integer LSB values (i.e., –FS + 0.5LSB,
–FS + 1.5LSB, –FS + 2.5LSB, . . . FS – 1.5LSB,
FS – 0.5LSB).The output is two’s complement binary
with 1LSB = [(+FS) – (–FS)]/4096 = 5V/4096 = 1.22mV.
In applications where absolute accuracy is important,
offset and full-scale errors can be adjusted to zero. Offset
error must be adjusted before full-scale error. Figure 10
shows the extra components required for full-scale error
adjustment. Zero offset is achieved by adjusting the offset
applied to the –A
IN
input. For zero offset error apply
–0.61mV (i.e., –0.5LSB) at +A
IN
and adjust the offset at
the –A
IN
input until the output code flickers between 0000
0000 0000 and 1111 1111 1111. For full-scale adjust-
ment, an input voltage of 2.49817V (FS – 1.5LSBs) is
applied to A
IN
and R2 is adjusted until the output code
flickers between 0111 1111 1110 and 0111 1111 1111.
BOARD LAYOUT AND BYPASSING
Wire wrap boards are not recommended for high resolu-
tion or high speed A/D converters. To obtain the best
performance from the LTC1410, a printed circuit board
with ground plane is required. Layout for the printed
circuit board should ensure that digital and analog signal
lines are separated as much as possible. Particular care
should be taken not to run any digital track alongside an
analog signal track or underneath the ADC. The analog
input should be screened by AGND.
ANALOG
INPUT
1410 F10
1
2
3
R4
100Ω
R2
50k
R3
47k
–5V
R6
24k
R1
50k
R5
47k
4
5
0.1µF
10µF
+A
IN
–A
IN
V
REF
REFCOMP
AGND
LTC1410
Figure 10. Offset and Full-Scale Adjust Circuit
INPUT VOLTAGE, (+A
IN
) – (–A
IN
) (V)
0V
OUTPUT CODE
–1
LSB
1410 F09
011...111
011...110
000...001
000...000
100...000
100...001
111...110
1
LSB
BIPOLAR
ZERO
111...111
FS – LSB–FS
FS = 2.5V
1LSB =
2FS
4096
Figure 9. LTC1410 Transfer Characteristics
12
LTC1410
APPLICATIONS INFORMATION
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High quality tantalum and ceramic bypass capacitors
should be used at the V
DD
, V
SS
and REFCOMP pins as
shown in the Typical Application on the first page of this
data sheet. Bypass capacitors must be located as close to
the pins as possible. The traces connecting the pins and
bypass capacitors must be kept short and should be made
as wide as possible.
The LTC1410 has differential inputs to minimize noise
coupling. Common mode noise on the +A
IN
and –A
IN
leads will be rejected by the input CMRR. The –A
IN
input
can be used as a ground sense for the +A
IN
input; the
LTC1410 will hold and convert the difference voltage
between + A
IN
and – A
IN
. The leads to + A
IN
(Pin 1) and – A
IN
(Pin 2) should be kept as short as possible. In applications
where this is not possible, the +A
IN
and – A
IN
traces should
be run side by side to equalize coupling.
A single point analog ground separate from the logic
system ground should be established with an analog
ground plane at Pin 5 (AGND) or as close as possible to the
ADC. Pin 14 and Pin 19 (ADC’s DGND) and all other analog
grounds should be connected to this single analog ground
point. No other digital grounds should be connected to this
analog ground point. Low impedance analog and digital
power supply common returns are essential to low noise
operation of the ADC and the foil width for these tracks
should be as wide as possible. In applications where the
ADC data outputs and control signals are connected to a
continuously active microprocessor bus, it is possible to
get errors in the conversion results. These errors are due
to feedthrough from the microprocessor to the successive
approximation comparator. The problem can be elimi-
nated by forcing the microprocessor into a wait state
during conversion or by using three-state buffers to iso-
late the ADC data bus.
DIGITAL INTERFACE
The A/D converter is designed to interface with micropro-
cessors as a memory mapped device. The CS and RD
control inputs are common to all peripheral memory
interfacing. A separate CONVST is used to initiate a con-
version.
Internal Clock
The A/D converter has an internal clock that eliminates the
need of synchronization between the external clock and
the CS and RD signals found in other ADCs. The internal
clock is factory trimmed to achieve a typical conversion
time of 0.65µs and a maximum conversion time over the
full operating temperature range of 0.75µs. No external
adjustments are required. The guaranteed maximum ac-
quisition time is 100ns. In addition, throughput time of
800ns and a minimum sampling rate of 1.25Msps is
guaranteed.
1410 F11
DIGITAL
SYSTEM
0.1µF
ANALOG
INPUT
CIRCUITRY
4
2
26 1914
1
0.1µF
10µF
10µF
+
–
0.1µF
28 27
10µF
+A
IN
–A
IN
AGND
REFCOMP
AV
DD
V
SS
DV
DD
DGND OGND
LTC1410
Figure 11. Power Supply Grounding Practice
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LTC1410CSW#PBF

Mfr. #:
Buy LTC1410CSW#PBF
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 12-B, 1.25Msps, Smpl A/D Conv w/ SD
Lifecycle:
New from this manufacturer.
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