4
LTC1410
POWER REQUIRE E TS
W
U
The denotes specifications which apply over the full operating temperature range,
otherwise specifications are at T
A
= 25°C. (Note 5)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
P
D
Power Dissipation 160 230 mW
Nap Mode SHDN = 0V, NAP/SLP = 5V 7.5 12 mW
Sleep Mode SHDN = 0V, NAP/SLP = 0V 0.01 1 mW
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
f
SAMPLE(MAX)
Maximum Sampling Frequency 1.25 MHz
t
CONV
Conversion Time 650 750 ns
t
ACQ
Acquisition Time 50 100 ns
t
ACQ+CONV
Throughput Time 800 ns
(Acquisition + Conversion)
t
1
CS to RD Setup Time (Notes 9, 10) 0ns
t
2
CS to CONVSTSetup Time (Notes 9, 10) 10 ns
t
3
NAP/SLPto SHDNSetup Time (Notes 9, 10) 10 ns
t
4
SHDN to CONVST Wake-Up Time (Note 10) 200 ns
t
5
CONVST Low Time (Notes 10, 11) 40 ns
t
6
CONVST to BUSY Delay C
L
= 25pF 10 ns
50 ns
t
7
Data Ready Before BUSY 20 35 ns
15 ns
t
8
Delay Between Conversions (Note 10) 40 ns
t
9
Wait Time RD After BUSY (Note 10) –5 ns
t
10
Data Access Time After RD C
L
= 25pF 15 25 ns
35 ns
C
L
= 100pF 20 35 ns
50 ns
t
11
Bus Relinquish Time 820 ns
Commercial 25 ns
Industrial
30 ns
t
12
RD Low Time t
10
ns
t
13
CONVST High Time 40 ns
t
14
Aperture Delay of Sample-and-Hold 1.5 ns
TI I G CHARACTERISTICS
W
U
The denotes specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25°C. (Note 5)
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 8: Bipolar offset is the offset voltage measured from –0.5LSB when
the output code flickers between 0000 0000 0000 and 1111 1111 1111.
Note 9: Guaranteed by design, not subject to test.
Note 10: Recommended operating conditions.
Note 11: The falling CONVST edge starts a conversion. If CONVST returns
high at a critical point during the conversion it can create small errors. For
best results ensure that CONVST returns high either within 425ns after the
start of the conversion or after BUSY rises.
Note 12: Signal-to-noise ratio (SNR) is measured at 100kHz and distortion
is measured at 600kHz. These results are used to calculate signal-to-noise
plus distortion (SINAD).
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to ground with DGND, OGND
and AGND wired together unless otherwise noted.
Note 3: When these pin voltages are taken below V
SS
or above V
DD
, they
will be clamped by internal diodes. This product can handle input currents
greater than 100mA below V
SS
or above V
DD
without latchup.
Note 4: When these pin voltages are taken below V
SS
, they will be clamped
by internal diodes. This product can handle input currents greater than
100mA below V
SS
without latchup. These pins are not clamped to V
DD
.
Note 5: V
DD
= 5V, V
SS
= –5V, f
SAMPLE
= 1.25MHz, t
r
= t
f
= 5ns unless
otherwise specified.
Note 6: Linearity, offset and full-scale specifications apply for a single-
ended +A
IN
input with –A
IN
grounded.
5
LTC1410
TYPICAL PERFORMANCE CHARACTERISTICS
UW
S/(N + D) vs Input Frequency
and Amplitude
Distortion vs Input Frequency
INPUT FREQUENCY (Hz)
1k
SIGNAL/(NOISE + DISTORTION) (dB)
80
70
60
50
40
30
20
10
0
10k 100k
1410 G01
1M 10M
V
IN
= 0dB
V
IN
= –20dB
V
IN
= –60dB
f
SAMPLE
= 1.25MHz
INPUT FREQUENCY (Hz)
1k
AMPLITUDE (dB BELOW THE FUNDAMENTAL)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
100
10k 100k
1410 G03
1M 10M
THD
2ND
3RD
Spurious-Free Dynamic Range vs
Input Frequency
Integral Nonlinearity vs
Output Code
Differential Nonlinearity vs
Output Code
INPUT FREQUENCY (Hz)
10k
SPURIOUS-FREE DYNAMIC RANGE (dB)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
100
100k 1M 10M
1410 G04
Input Common Mode Rejection
vs Input Frequency
INPUT FREQUENCY (Hz)
1k
COMMON MODE REJECTION (dB)
80
70
60
50
40
30
20
10
0
10k 100k
1410 G09
1M 10M
Signal-to-Noise Ratio vs
Input Frequency
INPUT FREQUENCY (Hz)
1k
SIGNAL-TO-NOISE RATIO (dB)
80
70
60
50
40
30
20
10
0
10k 100k
1410 G02
1M 10M
Intermodulation Distortion Plot
FREQUENCY (kHz)
0
AMPLITUDE (dB)
0
–20
–40
–60
–80
100
120
100
200 300 400
1410 G05
500 600
f
SAMPLE
= 1.25MHz
f
IN1
= 88.19580078kHz
f
IN2
= 111.9995117kHz
Power Supply Feedthrough
vs Ripple Frequency
RIPPLE FREQUENCY (Hz)
AMPLITUDE OF POWER SUPPLY FEEDTHROUGH (dB)
0
–20
–40
–60
–80
100
120
1k 100k 1M 10M
1410 G08
10k
V
RIPPLE
= 0.1V
V
SS
V
DD
DGND
OUTPUT CODE
0
INL ERROR (LSB)
4096
1410 G07
1024
2048
3072
1.0
0.5
0
0.5
1.0
512 1536 2560
3504
OUTPUT CODE
0
DNL ERROR (LSB)
4096
1410 G06
1024
2048
3072
1.0
0.5
0
0.5
1.0
512 1536 2560
3504
6
LTC1410
PI FU CTIO S
UU U
+A
IN
(Pin 1): Positive Analog Input, ±2.5V.
–A
IN
(Pin 2): Negative Analog Input, ±2.5V.
V
REF
(Pin 3): 2.50V Reference Output.
REFCOMP (Pin 4): 4.06V Reference Bypass Pin. By-
pass to AGND with 10µF tantalum in parallel with 0.1µF
ceramic.
AGND (Pin 5): Analog Ground.
D11 to D4 (Pins 6 to 13): Three-State Data Outputs.
DGND (Pin 14): Digital Ground for Internal Logic. Tie to
AGND.
D3 to D0 (Pins 15 to 18): Three-State Data Outputs.
OGND (Pin 19): Digital Ground for Output Drivers. Tie
to AGND.
NAP/SLP (Pin 20): Power Shutdown Mode. Selects the
mode invoked by the SHDN pin. Low selects Sleep
mode and high selects quick wake-up Nap mode.
FU CTIO AL BLOCK DIAGRA
UU W
12-BIT CAPACITIVE DAC
COMPREF AMP
2k
2.5V REF
REFCOMP
(4V)
C
SAMPLE
C
SAMPLE
D11
D0
BUSY
CONTROL LOGIC
CSCONVST RDSHDN
INTERNAL
CLOCK
NAP/SLP
ZEROING SWITCHES
DV
DD
V
SS
AV
DD
+A
IN
–A
IN
V
REF
AGND
DGND
12
LTC1410 • BD
+
SUCCESSIVE APPROXIMATION
REGISTER
OUTPUT LATCHES
SHDN (Pin 21): Power Shutdown Input. A low logic
level will invoke the Shutdown mode selected by the
NAP/SLP pin.
RD (Pin 22): Read Input. This enables the output
drivers when CS is low.
CONVST (Pin 23): Conversion Start Signal. This active
low signal starts a conversion on its falling edge.
CS (Pin 24): The Chip Select input must be low for the
ADC to recognize CONVST and RD inputs.
BUSY (Pin 25): The BUSY output shows the converter
status. It is low when a conversion is in progress. Data
valid on the rising edge of BUSY.
V
SS
(Pin 26):5V Negative Supply. Bypass to AGND
with 10µF tantalum in parallel 0.1µF ceramic.
DV
DD
(Pin 27): 5V Positive Supply. Short to Pin 28.
AV
DD
(Pin 28): 5V Positive Supply. Bypass to AGND
with 10µF tantalum in parallel with 0.1µF ceramic.

LTC1410CSW#PBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 12-B, 1.25Msps, Smpl A/D Conv w/ SD
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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