7
LTC1410
TEST CIRCUITS
APPLICATIONS INFORMATION
WUU
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CONVERSION DETAILS
The LTC1410 uses a successive approximation algorithm
and an internal sample-and-hold circuit to convert an
analog signal to a 12-bit parallel output. The ADC is
complete with a precision reference and an internal clock.
The control logic provides easy interface to microproces-
sors and DSPs. (Please refer to the Digital Interface
section for the data format.)
Conversion start is controlled by the CS and CONVST
inputs. At the start of the conversion the successive
approximation register (SAR) is reset. Once a conversion
cycle has begun it cannot be restarted.
During the conversion, the internal differential 12-bit
capacitive DAC output is sequenced by the SAR from the
Most Significant Bit (MSB) to the Least Significant Bit
(LSB). Referring to Figure 1, the +A
IN
and –A
IN
inputs are
connected to the sample-and-hold capacitors (C
SAMPLE
)
during the acquire phase and the comparator offset is
nulled by the zeroing switches. In this acquire phase, a
minimum duration of 100ns will provide enough time for
the sample-and-hold capacitors to acquire the analog
signal. During the convert phase the comparator zeroing
switches open, putting the comparator into compare
mode. The input switches connect the C
SAMPLE
capacitors
to ground, transferring the differential analog input charge
1k C
L
C
L
DBN
(A) Hi-Z TO V
OH
AND V
OL
TO V
OH
(B) Hi-Z TO V
OL
AND V
OH
TO V
OL
DBN
1k
5V
1410 TC01
1k 100pF 100pF
DBN
(A) V
OH
TO Hi-Z (B) V
OL
TO Hi-Z
DBN
1k
5V
1410 TC02
Load Circuits for Access Timing
Load Circuits for Output Float Delay
onto the summing junctions. This input charge is succes-
sively compared with the binarily-weighted charges sup-
plied by the differential capacitive DAC. Bit decisions are
made by the high speed comparator. At the end of a
conversion, the differential DAC output balances the +A
IN
and –A
IN
input charges. The SAR contents (a 12-bit data
word) which represent the difference of +A
IN
and –A
IN
are
loaded into the 12-bit output latches.
SAMPLE
HOLD
+C
SAMPLE
–C
SAMPLE
D11
D0
ZEROING SWITCHES
+A
IN
+C
DAC
+V
DAC
–C
DAC
–V
DAC
–A
IN
12
1410 F01
COMP
+
OUTPUT
LATCHES
SAR
SAMPLE
HOLD
HOLD
HOLD
Figure 1. Simplified Block Diagram
8
LTC1410
APPLICATIONS INFORMATION
WUU
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DYNAMIC PERFORMANCE
The LTC1410 has excellent high speed sampling capabil-
ity. Fast Four Transform (FFT) test techniques are used to
test the ADC’s frequency response, distortion and noise at
the rated throughput. By applying a low distortion sine
wave and analyzing the digital output using an FFT algo-
rithm, the ADC’s spectral content can be examined for
frequencies outside the fundamental.
FREQUENCY (kHz)
0
AMPLITUDE (dB)
0
–20
–40
–60
–80
100
120
100
200 300 400
1410 F02a
500 600
f
SAMPLE
= 1.25MHz
f
IN
= 100.098kHz
SFDR = 90.1dB
SINAD = 72.4dB
FREQUENCY (kHz)
0
AMPLITUDE (dB)
0
–20
–40
–60
–80
100
120
100
200 300 400
1410 F02b
500 600
f
SAMPLE
= 1.25MHz
f
IN
= 599.975kHz
SFDR = 84.7dB
SINAD = 71.7dB
Figure 2b. LTC1410 Nonaveraged 4096 Point FFT, 600kHz Input
Figure 2a. LTC1410 Nonaveraged 4096 Point FFT, 100kHz Input
to frequencies from above DC and below half the sampling
frequency. Figures 2a and 2b shows a typical spectral
content with a 1.25MHz sampling rate for 100kHz and
600kHz inputs. The dynamic performance is excellent for
input frequencies up to the Nyquist limit of 625kHz and
beyond.
Effective Number of Bits
The Effective Number of Bits (ENOBs) is a measurement
of the resolution of an ADC and is directly related to the
S/(N + D) by the equation:
N = [S/(N + D) – 1.76]/6.02
where N is the effective number of bits of resolution and
S/(N + D) is expressed in dB. At the maximum sampling
rate of 1.25MHz the LTC1410 maintains very good ENOBs
up to the Nyquist input frequency of 625kHz and beyond.
Refer to Figure 3.
Signal-to-Noise Ratio
The Signal-to-Noise plus Distortion ratio [S/(N + D)] is the
ratio between the RMS amplitude of the fundamental input
frequency to the RMS amplitude of all other frequency
components at the ADC output. The output is band limited
INPUT FREQUENCY (Hz)
2
EFFECTIVE BITS
S/(N + D) (dB)
4
6
8
10
10k 100k 1M 10M
LTC1410 • TA02
0
1k
12 74
68
62
56
50
f
SAMPLE
= 1.25MHz
NYQUIST
Figure 3. Effective Bits and Signal/(Noise + Distortion)
vs Input Frequency
Total Harmonic Distortion (THD)
Total harmonic distortion is the ratio of the RMS sum of all
harmonics of the input signal to the fundamental itself. The
out-of-band harmonics alias into the frequency band
between DC and half the sampling frequency. THD is
expressed as:
THD
VV
=
+++
20
3
2
4
2
log
V . . .V
V
2
2
n
2
1
9
LTC1410
APPLICATIONS INFORMATION
WUU
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where V
1
is the RMS amplitude of the fundamental fre-
quency and V
2
through V
n
are the amplitudes of the
second through nth harmonics. THD vs Input Frequency is
shown in Figure 4. The LTC1410 has good distortion
performance up to the Nyquist frequency and beyond.
FREQUENCY (MHz)
0
AMPLITUDE (dB)
0
–20
–40
–60
–80
100
120
100
(f
b
–f
a
)
(f
a
+f
b
)
(2f
a
+f
b
)
(f
a
+2f
b
)
(f
a
)
(2f
a
)
(f
b
)
(2f
b
–f
a
)
200 300 400
1410 F05
500 600
(2f
b
)
f
SAMPLE
= 1.25MHz
f
IN1
= 88.19580078kHz
f
IN2
= 111.9995117kHz
(2f
a
–f
b
)
(3f
a
)
(3f
b
)
Figure 5. Intermodulation Distortion Plot
Peak Harmonic or Spurious Noise
The peak harmonic or spurious noise is the largest spec-
tral component excluding the input signal and DC. This
value is expressed in decibel relative to the RMS value of
a full-scale input signal.
Full Power and Full Linear Bandwidth
The full power bandwidth is that input frequency at which
the amplitude of the reconstructed fundamental is re-
duced by 3dB for a full-scale input signal.
The full linear bandwidth is the input frequency at which
the S/(N + D) has dropped to 68dB (11 effective bits). The
LTC1410 has been designed to optimize input bandwidth,
allowing the ADC to undersample input signals with fre-
quencies above the converter’s Nyquist frequency. The
noise floor stays very low at high frequencies; S/(N + D)
does not become dominated by distortion until frequen-
cies far beyond Nyquist.
Driving the Analog Input
The differential analog inputs of the LTC1410 are easy to
drive. The inputs may be driven differentially or as a
single-ended input (i.e., the –A
IN
input is grounded). The
+A
IN
and –A
IN
inputs are sampled at the same instant.
Any unwanted signal that is common mode to both
inputs will be reduced by the common mode rejection of
the sample-and-hold circuit. The inputs draw only one
small current spike while charging the sample-and-hold
INPUT FREQUENCY (Hz)
1k
AMPLITUDE (dB BELOW THE FUNDAMENTAL)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
100
10k 100k
1410 G03
1M 10M
THD
2ND
3RD
Figure 4. Distortion vs Input Frequency
Intermodulation Distortion (IMD)
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce Intermodulation Distortion in addition to THD.
IMD is the change in one sinusoidal input caused by the
presence of another sinusoidal input at a different
frequency.
If two pure sine waves of frequencies f
a
and f
b
are applied
to the ADC input, nonlinearities in the ADC transfer func-
tion can create distortion products at the sum and differ-
ence frequencies of mf
a
± nf
b
, where m and n = 0, 1, 2, 3,
etc. For example, the 2nd order IMD terms include
(f
a
+ f
b
). If the two input sine waves are equal in magnitude,
the value (in decibels) of the 2nd order IMD products can
be expressed by the following formula:
IMD f f
f
Amplitude at
ab
b
+
()
=
±
()
20 log
Amplitude at f
f
a
a

LTC1410CSW#PBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 12-B, 1.25Msps, Smpl A/D Conv w/ SD
Lifecycle:
New from this manufacturer.
Delivery:
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