Dual LVCMOS / LVTTL-to-Differential
HSTL Translator
85222-01
DATASHEET
85222-01 REVISION A 5/7/15 1 ©2015 Integrated Device Technology, Inc.
The 85222-01 is a Dual LVCMOS / LVTTL-to-
Differential HSTL translator. The 85222-01 has two
single ended clock inputs. The single ended clock input
accepts LVCMOS or LVTTL input levels and translates
them to HSTL levels. The small outline 8-pin SOIC package
makes this device ideal for applications where space, high
performance and low power are important.
GENERAL DESCRIPTION F
EATURES
Two differential HSTL outputs
CLK0, CLK1 LVCMOS/LVTTL clock inputs
CLK0 and CLK1 can accept the following input levels:
LVCMOS or LVTTL
Maximum output frequency: 350MHz
Part-to-part skew: 375ps (maximum)
Propagation delay: 1075ps (maximum)
V
OH
: 1.4V (maximum)
Full 3.3V and 2.5V operating supply voltage
0°C to 70°C ambient operating temperature
Industrial temperature information available upon request
Available in lead-free RoHS-compliant package
BLOCK DIAGRAM PIN ASSIGNMENT
85222-01
8-Lead SOIC
3.90mm x 4.92mm x 1.37mm body package
M Package
Top View
Q0
nQ0
Q1
nQ1
1
2
3
4
Q0
nQ0
Q1
nQ1
CLK0
CLK1
VDD
CLK0
CLK1
GND
8
7
6
5
DUAL LVCMOS / LVTTL-TODIFFERENTIAL
HSTL TRANSLATOR
85222-01 DATA SHEET
2 REVISION A 5/7/15
TABLE 1. PIN DESCRIPTIONS
TABLE 2. PIN CHARACTERISTICS
Number Name Type Description
1, 2 Q0, nQ0 Output Differential output pair. HSTL interface levels.
3, 4 Q1, nQ1 Output Differential output pair. HSTL interface levels.
5 GND Power Power supply ground.
6 CLK1 Input Pullup LVCMOS / LVTTL clock input.
7 CLK0 Input Pullup LVCMOS / LVTTL clock input.
8V
DD
Power Positive supply pin.
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
NOTE: Unused output pairs must be terminated.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 4 pF
R
PULLUP
Input Pullup Resistor 51
kΩ
R
PULLDOWN
Input Pulldown Resistor 51
kΩ
REVISION A 5/7/15
85222-01 DATA SHEET
3 DUAL LVCMOS / LVTTL-TODIFFERENTIAL
HSTL TRANSLATOR
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, V
DD
= 3.3V±5% OR V
DD
= 2.5V±5%, TA = 0°C TO 70°C
TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, V
DD
= 3.3V±5% OR V
DD
= 2.5V±5%, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
DD
Positive Supply Voltage 3.135 3.3 3.465 V
V
DD
Positive Supply Voltage 2.375 2.5 2.625 V
I
DD
Power Supply Current 35 mA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
IH
Input High Voltage CLK0, CLK1 2 V
DD
+ 0.3 V
V
IL
Input Low Voltage CLK0, CLK1 -0.3 1.3 V
I
IH
Input High Current CLK0, CLK1
V
DD
= V
IN
= 3.465V
A
V
DD
= V
IN
= 2.625V
I
IL
Input Low Current CLK0, CLK1
V
DD
= 3.465, V
IN
= 0V
-150 µA
V
DD
= 2.625, V
IN
= 0V
TABLE 3C. HSTL DC CHARACTERISTICS, V
DD
= 3.3V±5% OR V
DD
= 2.5V±5%, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
OH
Output High Voltage; NOTE 1 1 1.4 V
V
OL
Output Low Voltage; NOTE 1
V
DD
= 3.3V±5% 0 0.4 V
V
DD
= 2.5V±5% 0 0.55 V
V
SWING
Peak-to-Peak Output Voltage Swing
V
DD
= 3.3V±5% 0.6 1.4 V
V
DD
= 2.5V±5% 0.45 1.4 V
NOTE 1: Outputs terminated with 50Ω to GND.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5V
Outputs, I
O
Continuous Current 50mA
Surge Current 100mA
Package Thermal Impedance, θ
JA
112.7°C/W (0 lfpm)
Storage Temperature, T
STG
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifi cations only. Functional
operation of product at these conditions or any conditions
beyond those listed in the DC Characteristics or AC Charac-
teristics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.

85222AM-01LF

Mfr. #:
Manufacturer:
Description:
Translation - Voltage Levels DUAL 1 HSTL OUT BUFFER
Lifecycle:
New from this manufacturer.
Delivery:
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