74ABT544 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 3 November 2011 9 of 16
NXP Semiconductors
74ABT544
Octal latched transceiver with dual enable; 3-state
V
M
=1.5V
The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig 9. Data set-up and hold times and latch enable pulse width
001aae905
V
M
An, Bn
LEAB, LEBA,
EAB, EBA
V
M
V
M
V
M
V
M
V
M
t
su(H)
t
h(H)
t
su(L)
t
h(L)
t
WL
V
I
GND
V
I
GND
a. Input pulse definition b. Test circuit
Test data is given in Table 8.
Definitions test circuit:
R
L
= Load resistor.
C
L
= Load capacitance including jig and probe capacitance.
R
T
= Termination resistance should be equal to output impedance Z
o
of the pulse generator.
V
EXT
= Test voltage for switching times.
Fig 10. Load circuitry for switching times
001aai298
V
M
V
M
t
W
t
W
10 %
90 % 90 %
0 V
V
I
V
I
negative
pulse
positive
pulse
0 V
V
M
V
M
90 %
10 %
90 %
10 % 10 %
t
f
t
r
t
r
t
f
V
EXT
V
CC
V
I
V
O
mna616
DUT
C
L
R
T
R
L
R
L
G
Table 8. Test data
Input Load V
EXT
V
I
f
I
t
W
t
r
, t
f
C
L
R
L
t
PHL
, t
PLH
t
PZH
, t
PHZ
t
PZL
, t
PLZ
3.0 V 1 MHz 500 ns 2.5 ns 50 pF 500 open open 7.0 V
