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74ABT544D,623

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
74ABT544 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 3 November 2011 6 of 16
NXP Semiconductors
74ABT544
Octal latched transceiver with dual enable; 3-state
[1] For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.
[2] This parameter is valid for any V
CC
between 0 V and 2.1 V, with a transition time of up to 10 ms. From V
CC
= 2.1 V to V
CC
= 5 V 10 %,
a transition time of up to 100 s is permitted.
[3] Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
[4] This is the increase in supply current for each input at 3.4 V.
10. Dynamic characteristics
V
OL(pu)
power-up LOW-level
output voltage
V
CC
= 5.5 V; I
O
=1mA;
V
I
=GNDorV
CC
[1]
- 0.13 0.55 - 0.55 V
I
I
input leakage current V
CC
= 5.5 V; V
I
=GNDor 5.5V
control pins - 0.01 1.0 - 1.0 A
An, Bn - 5.0 100 - 100 A
I
OFF
power-off leakage
current
V
CC
= 0 V; V
I
or V
O
4.5 V - 5.0 100 - 100 A
I
O(pu/pd)
power-up/power-down
output current
V
CC
= 2.1 V; V
O
=0.5V;
V
I
=GNDor V
CC
;
OEAB,OEBAdon’t care
[2]
- 5.0 50 - 50 A
I
OZ
OFF-state output
current
V
CC
= 5.5 V; V
I
= V
IL
or V
IH
V
O
= 2.7 V - 5.0 50 - 50 A
V
O
= 0.5 V - 5.0 50 - 50 A
I
LO
output leakage current HIGH-state; V
O
=5.5V;
V
CC
=5.5V; V
I
=GNDor V
CC
-5.050 - 50A
I
O
output current V
CC
= 5.5 V; V
O
= 2.5 V
[3]
180 65 50 180 50 mA
I
CC
supply current V
CC
= 5.5 V; V
I
= GND or V
CC
outputs HIGH-state - 110 250 - 250 A
outputs LOW-state - 20 30 - 30 mA
outputs disabled - 110 250 - 250 A
I
CC
additional supply
current
per input pin; V
CC
= 5.5 V; one input
pin at 3.4 V, other inputs at V
CC
or
GND
[4]
- 0.3 1.5 - 1.5 mA
C
I
input capacitance V
I
= 0 V or V
CC
-4- - -pF
C
I/O
input/output
capacitance
outputs disabled; V
O
=0V orV
CC
-7- - -pF
Table 6. Static characteristics
…continued
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 C 40 C to +85 C Unit
Min Typ Max Min Max
Table 7. Dynamic characteristics
GND = 0 V; for test circuit, see Figure 10.
Symbol Parameter Conditions 25 C; V
CC
= 5.0 V 40 C to +85 C;
V
CC
= 5.0 V 0.5 V
Unit
Min Typ Max Min Max
t
PLH
LOW to HIGH
propagation delay
An to Bn or Bn to An; see Figure 5 1.7 3.0 3.8 1.7 4.7 ns
LEBA
to An or LEAB to Bn; see Figure 6 2.1 3.5 4.2 2.1 5.2 ns
74ABT544 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 3 November 2011 7 of 16
NXP Semiconductors
74ABT544
Octal latched transceiver with dual enable; 3-state
11. Waveforms
t
PHL
HIGH to LOW
propagation delay
An to Bn or Bn to An; see Figure 5 2.4 3.6 4.5 2.4 5.2 ns
LEBA
to An or LEAB to Bn; see Figure 6 3.0 4.4 5.3 3.0 6.2 ns
t
PZH
OFF-state to HIGH
propagation delay
OEBA to An, OEAB to Bn; see Figure 7 1.8 3.0 3.9 1.8 4.7 ns
EBA
to An, EAB to Bn; see Figure 7 1.9 3.4 4.1 1.9 5.0 ns
t
PZL
OFF-state to LOW
propagation delay
OEBA to An, OEAB to Bn; see Figure 8 2.9 4.2 5.2 2.9 6.1 ns
EBA
to An, EAB to Bn; see Figure 8 3.1 4.6 5.5 3.1 6.5 ns
t
PHZ
HIGH to OFF-state
propagation delay
OEBA to An, OEAB to Bn; see Figure 7 2.0 3.3 4.3 2.0 4.9 ns
EBA
to An, EAB to Bn; see Figure 7 2.1 3.4 4.5 2.1 5.2 ns
t
PLZ
LOW to OFF-state
propagation delay
OEBA to An, OEAB to Bn; see Figure 8 2.0 2.8 5.8 2.0 6.3 ns
EBA
to An, EAB to Bn; see Figure 8 2.0 3.0 6.2 2.0 6.7 ns
t
su(H)
set-up time HIGH An to LEAB, Bn to LEBA; see Figure 9 3.0 1.5 - 3.0 - ns
An to EAB
, Bn to EBA; see Figure 9 3.0 1.5 - 3.0 - ns
t
su(L)
set-up time LOW An to LEAB, Bn to LEBA; see Figure 9 3.0 0.6 - 3.0 - ns
An to EAB
, Bn to EBA; see Figure 9 3.0 0.6 - 3.0 - ns
t
h(H)
hold time HIGH LEAB to An, LEBA to Bn; see Figure 9 +0.5 0.3 - 0.5 - ns
EAB
to An, EBA to Bn; see Figure 9 +0.5 0.2 - 0.5 - ns
t
h(L)
hold time LOW LEAB to An, LEBA to Bn; see Figure 9 +0.5 1.3 - 0.5 - ns
EAB
to An, EBA to Bn; see Figure 9 +0.5 1.3 - 0.5 - ns
t
WL
pulse width LOW latch enable; see Figure 9 3.5 1.8 - 3.5 - ns
Table 7. Dynamic characteristics
…continued
GND = 0 V; for test circuit, see Figure 10.
Symbol Parameter Conditions 25 C; V
CC
= 5.0 V 40 C to +85 C;
V
CC
= 5.0 V 0.5 V
Unit
Min Typ Max Min Max
V
M
=1.5V
V
OL
and V
OH
are typical voltage output levels that occur with the output load.
Fig 5. Propagation delay input (An, Bn) to output (Bn, An)
001aac759
V
OL
V
OH
V
M
V
M
t
PHL
t
PLH
V
M
V
M
An, Bn
V
I
GND
Bn, An
74ABT544 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 3 November 2011 8 of 16
NXP Semiconductors
74ABT544
Octal latched transceiver with dual enable; 3-state
V
M
=1.5V
V
OL
and V
OH
are typical voltage output levels that occur with the output load.
Fig 6. Propagation delay latch enable (LEAB, LEBA) to output (An, Bn)
001aac761
V
OL
V
OH
V
I
V
M
V
M
t
PLH
t
PHL
V
M
V
M
GND
LEBA, LEAB
An, Bn
V
M
=1.5V
V
OH
is a typical voltage output level that occurs with the output load.
Fig 7. Propagation delay 3-state output enable to HIGH-level and output disable from HIGH-level
001aae907
V
M
V
M
V
OH
− 0.3 V
V
OH
GND
V
I
GND
V
M
t
PHZ
t
PZH
An, Bn
OEAB, OEBA,
EAB, EBA
V
M
=1.5V
V
OL
is a typical voltage output level that occurs with the output load.
Fig 8. Propagation delay 3-state output enable to LOW-level and output disable from LOW-level
001aae906
V
M
V
M
3.5 V
V
OL
+ 0.3 V
V
M
t
PLZ
t
PZL
An, Bn
OEAB, OEBA,
EAB, EBA
V
OL
V
I
GND
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74ABT544D,623

Mfr. #:
Buy 74ABT544D,623
Manufacturer:
NXP Semiconductors
Description:
IC TRANSCVR INVERT 5.5V 24SO
Lifecycle:
New from this manufacturer.
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