ADSP-2189MKCAZ-300 Datasheet ADSP-2189MBSTZ-266, ADSP-2189MKSTZ-300, ADSP-2189MKCAZ-300 | P10-P12

REV. A

ADSP-2189M

–7–

The master reset sets all internal stack pointers to the empty

stack condition, masks all interrupts and clears the MSTAT

request and the chip is configured for booting, the boot-loading

sequence is performed. The first instruction is fetched from

on-chip program memory location 0x0000 once boot loading

completes.

Power Supplies

The ADSP-2189M has separate power supply connections for

the internal (V

DDINT

) and external (V

DDEXT

) power supplies.

The internal supply must meet the 2.5 V requirement. The

external supply can be connected to either a 2.5 V or 3.3 V

supply. All external supply pins must be connected to the same

supply. All input and I/O pins can tolerate input voltages up

to 3.6 V regardless of the external supply voltage. This fea-

ture provides maximum flexibility in mixing 2.5 V and 3.3 V

components.

MODES OF OPERATION

Setting Memory Mode

Memory Mode selection for the ADSP-2189M is made during

chip reset through the use of the Mode C pin. This pin is multi-

plexed with the DSP’s PF2 pin, so care must be taken in how

the mode selection is made. The two methods for selecting the

value of Mode C are active and passive.

Table II. ADSP-2189M Modes of Operation

MODE D MODE C MODE B MODE A Booting Method

X 0 0 0 BDMA feature is used to load the first 32 program memory words from the

byte memory space. Program execution is held off until all 32 words have

been loaded. Chip is configured in Full Memory Mode.

X010No automatic boot operations occur. Program execution starts at external

memory location 0. Chip is configured in Full Memory Mode. BDMA can

still be used but the processor does not automatically use or wait for these

operations.

0100BDMA feature is used to load the first 32 program memory words from the

byte memory space. Program execution is held off until all 32 words have

been loaded. Chip is configured in Host Mode. IACK has active pull-down.

(REQUIRES ADDITIONAL HARDWARE).

0101IDMA feature is used to load any internal memory as desired. Program ex-

ecution is held off until internal program memory location 0 is written to.

Chip is configured in Host Mode.

IACK has active pull-down.

1100BDMA feature is used to load the first 32 program memory words from the

byte memory space. Program execution is held off until all 32 words have

been loaded. Chip is configured in Host Mode; IACK requires external pull-

down. (REQUIRES ADDITIONAL HARDWARE).

1101IDMA feature is used to load any internal memory as desired. Program ex-

ecution is held off until internal program memory location 0 is written to.

Chip is configured in Host Mode. IACK requires external pull-down.

NOTE

Considered as standard operating settings. Using these configurations allows for easier design and better memory management.

Passive Configuration involves the use a pull-up or pull-down

resistor connected to the Mode C pin. To minimize power

consumption, or if the PF2 pin is to be used as an output in the

DSP application, a weak pull-up or pull-down, on the order of

10 kΩ, can be used. This value should be sufficient to pull the

pin to the desired level and still allow the pin to operate as a

programmable flag output without undue strain on the processor’s

output driver. For minimum power consumption during power-

down, reconfigure PF2 to be an input, as the pull-up or pull-

down will hold the pin in a known state and will not switch.

Active Configuration involves the use of a three-statable ex-

ternal driver connected to the Mode C pin. A driver’s output

enable should be connected to the DSP’s RESET signal such

that it only drives the PF2 pin when RESET is active (low).

When RESET is deasserted, the driver should three-state, thus

allowing full use of the PF2 pin as either an input or output. To

minimize power consumption during power-down, configure

the programmable flag as an output when connected to a three-

stated buffer. This ensures that the pin will be held at a constant

level and will not oscillate should the three-state driver’s level

hover around the logic switching point.

IACK Configuration

Mode D = 0 and in host mode: IACK is an active, driven signal

and cannot be wire OR-ed.

REV. A

ADSP-2189M

–8–

Mode D = 1 and in host mode: IACK is an open source and

requires an external pull-down, but multiple IACK pins can be

wire OR-ed together.

MEMORY ARCHITECTURE

The ADSP-2189M provides a variety of memory and peripheral

interface options. The key functional groups are Program Memory,

Data Memory, Byte Memory and I/O. Refer to the following

figures and tables for PM and DM memory allocations in the

ADSP-2189M.

Program Memory

Program Memory, Full Memory Mode is a 24-bit-wide space

for storing both instruction op codes and data. The ADSP-2189M

has 32K words of Program Memory RAM on chip and the

capability of accessing up to two 8K external memory overlay

spaces using the external data bus.

Program Memory, Host Mode allows access to all internal

memory. External overlay access is limited by a single external

address line (A0). External program execution is not available in

host mode due to a restricted data bus that is 16-bits wide only.

Table III. PMOVLAY Bits

PMOVLAY Memory A13 A12:0

0, 4, 5 Internal Not Applicable Not Applicable

1 External 0 13 LSBs of Address

Overlay 1 Between 0x2000

and 0x3FFF

2 External 1 13 LSBs of Address

Overlay 2 Between 0x2000

and 0x3FFF

Data Memory

Data Memory, Full Memory Mode is a 16-bit-wide space

used for the storage of data variables and for memory-mapped

control registers. The ADSP-2189M has 48K words on Data

Memory RAM on-chip. Part of this space is used by 32 memory-

mapped registers. Support also exists for up to two 8K external

memory overlay spaces through the external data bus. All inter-

nal accesses complete in one cycle. Accesses to external memory

are timed using the wait-states specified by the DWAIT register

and the wait-state mode bit.

ACCESSIBLE WHEN

DMOVLAY = 2

ACCESSIBLE WHEN

DMOVLAY = 1

0ⴛ0000–

0ⴛ1FFF

0ⴛ0000–

0ⴛ1FFF

EXTERNAL

MEMORY

32 MEMORY–

MAPPED

REGISTERS

0ⴛ3FFF

0ⴛ2000

0ⴛ1FFF

INTERNAL

8160

WORDS

0ⴛ0000

DATA MEMORY

ADDRESS

INTERNAL

MEMORY

8K INTERNAL

DMOVLAY =

0, 4, 5, 6, 7

EXTERNAL 8K

DMOVLAY = 1, 2

0ⴛ3FE0

0ⴛ3FDF

DATA MEMORY

ACCESSIBLE WHEN

DMOVLAY = 7

ACCESSIBLE WHEN

DMOVLAY = 6

0ⴛ0000–

0ⴛ1FFF

0ⴛ0000–

0ⴛ1FFF

ACCESSIBLE WHEN

DMOVLAY = 5

ALWAYS

ACCESSIBLE

AT ADDRESS

0ⴛ2000 – 0ⴛ3FFF

ACCESSIBLE WHEN

DMOVLAY = 0

ACCESSIBLE WHEN

DMOVLAY = 4

0ⴛ0000–

0ⴛ1FFF

0ⴛ0000–

0ⴛ1FFF

0ⴛ0000–

0ⴛ1FFF

Figure 5. Data Memory Map

ACCESSIBLE WHEN

PMOVLAY = 2

ACCESSIBLE WHEN

PMOVLAY = 1

ACCESSIBLE WHEN

PMOVLAY = 5

ALWAYS

ACCESSIBLE

AT ADDRESS

0ⴛ0000 – 0ⴛ1FFF

ACCESSIBLE WHEN

PMOVLAY = 0

ACCESSIBLE WHEN

PMOVLAY = 4

INTERNAL

MEMORY

EXTERNAL

MEMORY

0ⴛ2000–

0ⴛ3FFF

0ⴛ2000–

0ⴛ3FFF

0ⴛ2000–

0ⴛ3FFF

0ⴛ2000–

0ⴛ3FFF

0ⴛ2000–

0ⴛ3FFF

PM (MODE B = 0)

8K INTERNAL

PMOVLAY = 0

8K EXTERNAL

PROGRAM MEMORY

MODE B = 1

ADDRESS

0ⴛ3FFF

0ⴛ2000

0ⴛ1FFF

0ⴛ0000

8K INTERNAL

PMOVLAY = 0, 4, 5

8K EXTERNAL

PMOVLAY = 1, 2

0ⴛ3FFF

0ⴛ2000

0ⴛ1FFF

8K INTERNAL

0ⴛ0000

PROGRAM MEMORY

MODE B = 0

ADDRESS

ACCESSIBLE WHEN

PMOVLAY = 1

RESERVED

INTERNAL

MEMORY

EXTERNAL

MEMORY

0ⴛ2000–

0ⴛ3FFF

0ⴛ0000–

0ⴛ1FFF

PM (MODE B = 1)

RESERVED

WHEN MODE B = 1, PMOVLAY MUST BE SET TO 0

SEE TABLE III FOR PMOVLAY BITS

ACCESSIBLE WHEN

PMOVLAY = 0

RESERVED

0ⴛ0000–

0ⴛ1FFF

Figure 4. Program Memory

REV. A

ADSP-2189M

–9–

Data Memory, Host Mode allows access to all internal

memory. External overlay access is limited by a single external

address line (A0).

Table IV. DMOVLAY Bits

PMOVLAY Memory A13 A12:0

0, 4, 5, 6, 7 Internal Not Applicable Not Applicable

1 External 0 13 LSBs of Address

Overlay 1 Between 0x2000

and 0x3FFF

2 External 1 13 LSBs of Address

Overlay 2 Between 0x2000

and 0x3FFF

Memory Mapped Registers (New to the ADSP-2189M)

The ADSP-2189M has three memory mapped registers that

differ from other ADSP-21xx Family DSPs. The slight modifi-

cations to these registers (Wait-State Control, Programmable

Flag and Composite Select Control and System Control) pro-

vide the ADSP-2189M’s wait-state and BMS control features.

DWAIT IOWAIT3 IOWAIT2 IOWAIT1 IOWAIT0

DM(0x3FFE)

WAIT STATE MODE SELECT (ADSP-2189M)

0 = NORMAL MODE (DWAIT, IOWAIT0-3 = N WAIT STATES, RANGING FROM 0 TO 7)

1 = 2N+1 MODE

(

DWAIT

IOWAIT0-3 = N WAIT STATES

RANGING FROM 0 TO 15

)

WAIT-STATE CONTROL

1111111111111111

1514131211109876543210

Figure 6. Wait-State Control Register (ADSP-2189M)

BMWAIT

(BIT-15, ADSP-2189M)

CMSSEL

0 = DISABLE CMS

1 = ENABLE CMS

DM(0x3FE6)

PROGRAMMABLE FLAG & COMPOSITE SELECT CONTROL

PFTYPE

0 = INPUT

1 = OUTPUT

(WHERE BIT: 11-IOM, 10BM, 9-DM, 8-PM)

1111111111111111

1514131211109876543210

Figure 7. Programmable Flag and Composite Select Con-

trol Register

RESERVED, ALWAYS = 0

(ADSP-2189M)

SPORT0 ENABLE

0 = DISABLE

1 = ENABLE

DM(0x3FFF)

SYSTEM CONTROL

SPORT1 ENABLE

0 = DISABLE

1 = ENABLE

SPORT1 CONFIGURE

0 = FI, FO, IRQ0, IRQ1, SCLK

1 = SPORT1

DISABLE BMS (ADSP-2189M)

0 = ENABLE BMS

1 = DISABLE BMS, EXCEPT WHEN MEMORY

STROBES ARE THREE-STATED

PWAIT

PROGRAM MEMORY

WAIT STATES

0000010000000111

1514131211109876543210

Figure 8. System Control Register

I/O Space (Full Memory Mode)

The ADSP-2189M supports an additional external memory

space called I/O space. This space is designed to support simple

connections to peripherals (such as data converters and external

registers) or to bus interface ASIC data registers. I/O space

supports 2048 locations of 16-bit-wide data. The lower eleven

bits of the external address bus are used; the upper three bits are

undefined. Two instructions were added to the core ADSP-2100

Family instruction set to read from and write to I/O memory

space. The I/O space also has four dedicated three-bit wait-state

registers, IOWAIT0–3, which, in combination with the wait-

state mode bit, specify up to 15 wait-states to be automatically

generated for each of four regions. The wait-states act on ad-

dress ranges as shown in Table V.

Table V. Wait-States

Address Range Wait-State Register

0x000–0x1FF IOWAIT0 and Wait-State Mode Select Bit

0x200–0x3FF IOWAIT1 and Wait-State Mode Select Bit

0x400–0x5FF IOWAIT2 and Wait-State Mode Select Bit

0x600–0x7FF IOWAIT3 and Wait-State Mode Select Bit

Composite Memory Select (CMS )

The ADSP-2189M has a programmable memory select signal

that is useful for generating memory select signals for memories

mapped to more than one space. The CMS signal is generated

to have the same timing as each of the individual memory

select signals (PMS, DMS, BMS, IOMS) but can combine

their functionality.

When set, each bit in the CMSSEL register causes the CMS

signal to be asserted when the selected memory select is as-

serted. For example, to use a 32K word memory to act as both

program and data memory, set the PMS and DMS bits in the

CMSSEL register and use the CMS pin to drive the chip select

of the memory, and use either DMS or PMS as the additional

address bit.

The CMS pin functions like the other memory select signals,

with the same timing and bus request logic. A 1 in the enable bit

causes the assertion of the CMS signal at the same time as the

selected memory select signal. All enable bits default to 1 at

reset, except the BMS bit.

Byte Memory Select (BMS)

The ADSP-2189M’s BMS disable feature combined with the

CMS pin lets you use multiple memories in the byte memory

space. For example, an EPROM could be attached to the BMS

select, and an SRAM could be connected to CMS. Because

BMS is enabled at reset, the EPROM would be used for boot-

ing. After booting, software could disable BMS and set the

CMS signal to respond to BMS, enabling the SRAM.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P35

ADSP-2189MKCAZ-300

Mfr. #:

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Manufacturer:

Analog Devices Inc.

Description:

Digital Signal Processors & Controllers - DSP, DSC 16B 75 MIPS 2.5V 2 Serial Prts Host Prt

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