ADSP-2189MKCAZ-300 Datasheet ADSP-2189MBSTZ-266, ADSP-2189MKSTZ-300, ADSP-2189MKCAZ-300 | P13-P15

REV. A

ADSP-2189M

–10–

Byte Memory

The byte memory space is a bidirectional, 8-bit-wide, external

memory space used to store programs and data. Byte memory is

accessed using the BDMA feature. The byte memory space

consists of 256 pages, each of which is 16K × 8.

The byte memory space on the ADSP-2189M supports read

and write operations as well as four different data formats. The

byte memory uses data bits 15:8 for data. The byte memory

uses data bits 23:16 and address bits 13:0 to create a 22-bit

address. This allows up to a 4 meg × 8 (32 megabit) ROM or

RAM to be used without glue logic. All byte memory accesses

are timed by the BMWAIT register and the wait-state mode bit.

Byte Memory DMA (BDMA, Full Memory Mode)

The Byte memory DMA controller allows loading and storing of

program instructions and data using the byte memory space.

The BDMA circuit is able to access the byte memory space

while the processor is operating normally and steals only one

DSP cycle per 8-, 16- or 24-bit word transferred.

BDMA CONTROL

BMPAGE BDMA

OVERLAY

BITS

BTYPE

BDIR

0 = LOAD FROM BM

1 = STORE TO BM

BCR

0 = RUN DURING BDMA

1 = HALT DURING BDMA

0000000000001000

1514131211109876543210

DM (0ⴛ3FE3)

Figure 9. BDMA Control Register

The BDMA circuit supports four different data formats which

are selected by the BTYPE register field. The appropriate num-

ber of 8-bit accesses are done from the byte memory space to

build the word size selected. Table VI shows the data formats

supported by the BDMA circuit.

Table VI. Data Formats

Internal

BTYPE Memory Space Word Size Alignment

00 Program Memory 24 Full Word

01 Data Memory 16 Full Word

10 Data Memory 8 MSBs

11 Data Memory 8 LSBs

Unused bits in the 8-bit data memory formats are filled with 0s.

The BIAD register field is used to specify the starting address

for the on-chip memory involved with the transfer. The 14-bit

BEAD register specifies the starting address for the external byte

memory space. The 8-bit BMPAGE register specifies the start-

ing page for the external byte memory space. The BDIR register

field selects the direction of the transfer. Finally, the 14-bit

BWCOUNT register specifies the number of DSP words to

transfer and initiates the BDMA circuit transfers.

BDMA accesses can cross page boundaries during sequential

addressing. A BDMA interrupt is generated on the completion

of the number of transfers specified by the BWCOUNT register.

The BWCOUNT register is updated after each transfer so it can

be used to check the status of the transfers. When it reaches

zero, the transfers have finished and a BDMA interrupt is gener-

ated. The BMPAGE and BEAD registers must not be accessed

by the DSP during BDMA operations.

The source or destination of a BDMA transfer will always be

on-chip program or data memory.

When the BWCOUNT register is written with a nonzero value

the BDMA circuit starts executing byte memory accesses with

wait-states set by BMWAIT. These accesses continue until the

count reaches zero. When enough accesses have occurred to

create a destination word, it is transferred to or from on-chip

memory. The transfer takes one DSP cycle. DSP accesses to

external memory have priority over BDMA byte memory

accesses.

The BDMA Context Reset bit (BCR) controls whether the

processor is held off while the BDMA accesses are occurring.

Setting the BCR bit to 0 allows the processor to continue opera-

tions. Setting the BCR bit to 1 causes the processor to stop

execution while the BDMA accesses are occurring, to clear the

context of the processor, and start execution at address 0 when

the BDMA accesses have completed.

The BDMA overlay bits specify the OVLAY memory blocks to

be accessed for internal memory.

The BMWAIT field, which has four bits on ADSP-2189M,

allows selection of up to 15 wait-states for BDMA transfers.

Internal Memory DMA Port (IDMA Port; Host Memory

Mode)

The IDMA Port provides an efficient means of communication

between a host system and the ADSP-2189M. The port is used

to access the on-chip program memory and data memory of the

DSP with only one DSP cycle per word overhead. The IDMA

port cannot, however, be used to write to the DSP’s memory-

mapped control registers. A typical IDMA transfer process is

described as follows:

1. Host starts IDMA transfer.

2. Host checks IACK control line to see if the DSP is busy.

3. Host uses IS and IAL control lines to latch either the DMA

starting address (IDMAA) or the PM/DM OVLAY selection

into the DSP’s IDMA control registers. If Bit 15 = 1, the

value of bits 7:0 represent the IDMA overlay: Bits 14:8 must

be set to 0. If Bit 15 = 0, the value of bits 13:0 represent the

starting address of internal memory to be accessed and Bit 14

reflects PM or DM for access.

4. Host uses IS and IRD (or IWR) to read (or write) DSP inter-

nal memory (PM or DM).

5. Host checks IACK line to see if the DSP has completed the

previous IDMA operation.

6. Host ends IDMA transfer.

REV. A

ADSP-2189M

–11–

The IDMA port has a 16-bit multiplexed address and data bus

and supports 24-bit program memory. The IDMA port is com-

pletely asynchronous and can be written while the ADSP-2189M

is operating at full speed.

The DSP memory address is latched and then automatically

incremented after each IDMA transaction. An external device

can therefore access a block of sequentially addressed memory

by specifying only the starting address of the block. This in-

creases throughput as the address does not have to be sent for

each memory access.

IDMA Port access occurs in two phases. The first is the IDMA

Address Latch cycle. When the acknowledge is asserted, a 14-bit

address and 1-bit destination type can be driven onto the bus by

an external device. The address specifies an on-chip memory

location, the destination type specifies whether it is a DM or

PM access. The falling edge of the IDMA address latch signal

(IAL) or the missing edge of the IDMA select signal (IS) latches

this value into the IDMAA register.

Once the address is stored, data can then be either read from, or

written to, the ADSP-2189M’s on-chip memory. Asserting the

select line (IS) and the appropriate read or write line (IRD and

IWR respectively) signals the ADSP-2189M that a particular

transaction is required. In either case, there is a one-processor-

cycle delay for synchronization. The memory access consumes

one additional processor cycle.

Once an access has occurred, the latched address is automati-

cally incremented and another access can occur.

Through the IDMAA register, the DSP can also specify the

starting address and data format for DMA operation. Asserting

the IDMA port select (IS) and address latch enable (IAL) di-

rects the ADSP-2189M to write the address onto the IAD0-14

bus into the IDMA Control Register. If Bit 15 is set to 0, IDMA

latches the address. If Bit 15 is set to 1, IDMA latches into the

OVLAY register. This register, shown below, is memory

mapped at address DM (0x3FE0). Note that the latched address

(IDMAA) cannot be read back by the host.

Refer to the following figures for more information on IDMA

and DMA memory maps.

IDMA CONTROL (U = UNDEFINED AT RESET)

DM(0ⴛ3FE0)

IDMAA ADDRESS

IDMAD DESTINATION MEMORY TYPE:

0 = PM

1 = DM

UUUUUUUUUUUUUUU

1514131211109876543210

IDMA OVERLAY

DM(0ⴛ3FE7)

RESERVED SET TO 0 ID DMOVLAY ID PMOVLAY

000000000000000

1514131211109876543210

Figure 10. IDMA Control/OVLAY Registers

ACCESSIBLE WHEN

PMOVLAY = 5

ALWAYS

ACCESSIBLE

AT ADDRESS

0ⴛ0000 – 0ⴛ1FFF

ACCESSIBLE WHEN

PMOVLAY = 0

ACCESSIBLE WHEN

PMOVLAY = 4

0ⴛ2000–

0ⴛ3FFF

0ⴛ2000–

0ⴛ3FFF

0ⴛ2000–

0ⴛ3FFF

DMA

PROGRAM MEMORY

OVLAY

NOTE: IDMA AND BDMA HAVEN SEPARATE

DMA CONTROL REGISTERS

DMA

DATA MEMORY

OVLAY

ACCESSIBLE WHEN

DMOVLAY = 7

ACCESSIBLE WHEN

DMOVLAY = 6

0ⴛ0000–

0ⴛ1FFF

0ⴛ0000–

0ⴛ1FFF

ACCESSIBLE WHEN

DMOVLAY = 5

ALWAYS

ACCESSIBLE

AT ADDRESS

0ⴛ2000 – 0ⴛ3FFF

ACCESSIBLE WHEN

DMOVLAY = 0

ACCESSIBLE WHEN

DMOVLAY = 4

0ⴛ0000–

0ⴛ1FFF

0ⴛ0000–

0ⴛ1FFF

0ⴛ0000–

0ⴛ1FFF

Figure 11. Direct Memory Access—PM and DM Memory

Maps

Bootstrap Loading (Booting)

The ADSP-2189M has two mechanisms to allow automatic

loading of the internal program memory after reset. The method

for booting is controlled by the Mode A, B and C configuration

bits.

When the MODE pins specify BDMA booting, the ADSP-2189M

initiates a BDMA boot sequence when reset is released.

The BDMA interface is set up during reset to the following

defaults when BDMA booting is specified: the BDIR, BMPAGE,

BIAD and BEAD registers are set to 0, the BTYPE register is

set to 0 to specify program memory 24-bit words, and the

BWCOUNT register is set to 32. This causes 32 words of on-

chip program memory to be loaded from byte memory. These

32 words are used to set up the BDMA to load in the remaining

program code. The BCR bit is also set to 1, which causes pro-

gram execution to be held off until all 32 words are loaded into

on-chip program memory. Execution then begins at address 0.

The ADSP-2100 Family development software (Revision 5.02

and later) fully supports the BDMA booting feature and can

generate byte memory space compatible boot code.

The IDLE instruction can also be used to allow the processor to

hold off execution while booting continues through the BDMA

interface. For BDMA accesses while in Host Mode, the ad-

dresses to boot memory must be constructed externally to the

ADSP-2189M. The only memory address bit provided by the

processor is A0.

IDMA Port Booting

The ADSP-2189M can also boot programs through its Internal

DMA port. If Mode C = 1, Mode B = 0, and Mode A = 1, the

ADSP-2189M boots from the IDMA port. IDMA feature can

load as much on-chip memory as desired. Program execution is

held off until on-chip program memory location 0 is written to.

REV. A

ADSP-2189M

–12–

Bus Request and Bus Grant

The ADSP-2189M can relinquish control of the data and ad-

dress buses to an external device. When the external device

requires access to memory, it asserts the bus request (BR) sig-

nal. If the ADSP-2189M is not performing an external memory

access, it responds to the active BR input in the following pro-

cessor cycle by:

• Three-stating the data and address buses and the PMS,

DMS, BMS, CMS, IOMS, RD, WR output drivers,

• Asserting the bus grant (BG) signal, and

• Halting program execution.

If Go Mode is enabled, the ADSP-2189M will not halt program

execution until it encounters an instruction that requires an

external memory access.

If the ADSP-2189M is performing an external memory access

when the external device asserts the BR signal, it will not three-

state the memory interfaces or assert the BG signal until the

processor cycle after the access completes. The instruction does

not need to be completed when the bus is granted. If a single

instruction requires two external memory accesses, the bus will

be granted between the two accesses.

When the BR signal is released, the processor releases the BG

signal, reenables the output drivers and continues program

execution from the point at which it stopped.

The bus request feature operates at all times, including when

the processor is booting and when RESET is active.

The BGH pin is asserted when the ADSP-2189M requires the

external bus for a memory or BDMA access, but is stopped.

The other device can release the bus by deasserting bus request.

Once the bus is released, the ADSP-2189M deasserts BG and

BGH and executes the external memory access.

Flag I/O Pins

The ADSP-2189M has eight general purpose programmable

input/output flag pins. They are controlled by two memory

mapped registers. The PFTYPE register determines the direc-

tion, 1 = output and 0 = input. The PFDATA register is used to

read and write the values on the pins. Data being read from a

pin configured as an input is synchronized to the ADSP-2189M’s

clock. Bits that are programmed as outputs will read the value

being output. The PF pins default to input during reset.

In addition to the programmable flags, the ADSP-2189M has

five fixed-mode flags, FLAG_IN, FLAG_OUT, FL0, FL1 and

FL2. FL0-FL2 are dedicated output flags. FLAG_IN and

FLAG_OUT are available as an alternate configuration of

SPORT1.

Note: Pins PF0, PF1, PF2 and PF3 are also used for device

configuration during reset.

INSTRUCTION SET DESCRIPTION

The ADSP-2189M assembly language instruction set has an

algebraic syntax that was designed for ease of coding and read-

ability. The assembly language, which takes full advantage of the

processor’s unique architecture, offers the following benefits:

• The algebraic syntax eliminates the need to remember cryp-

tic assembler mnemonics. For example, a typical arithmetic

add instruction, such as AR = AX0 + AY0, resembles a

simple equation.

• Every instruction assembles into a single, 24-bit word that

can execute in a single instruction cycle.

• The syntax is a superset ADSP-2100 Family assembly language

and is completely source-and-object-code-compatible with

other family members. Programs may need to be relocated to

utilize on-chip memory and conform to the ADSP-2189M’s

interrupt vector and reset vector map.

• Sixteen condition codes are available. For conditional jump,

call, return, or arithmetic instructions, the condition can be

checked and the operation executed in the same instruction

cycle.

• Multifunction instructions allow parallel execution of an

arithmetic instruction with up to two fetches or one write to

processor memory space during a single instruction cycle.

DESIGNING AN EZ-ICE-COMPATIBLE SYSTEM

The ADSP-2189M has on-chip emulation support and an ICE-

Port, a special set of pins that interface to the EZ-ICE. These

features allow in-circuit emulation without replacing the target

system processor by using only a 14-pin connection from the

target system to the EZ-ICE. Target systems must have a 14-pin

connector to accept the EZ-ICE’s in-circuit probe, a 14-pin

plug.

Issuing the chip reset command during emulation causes the

DSP to perform a full chip reset, including a reset of its memory

mode. Therefore, it is vital that the mode pins are set correctly

PRIOR to issuing a chip reset command from the emulator user

interface. If you are using a passive method of maintaining

mode information (as discussed in Setting Memory Modes),

then it does not matter that the mode information is latched by

an emulator reset. However, if using the RESET pin as a

method of setting the value of the mode pins, the effects of an

emulator reset must be taken into consideration.

One method of ensuring that the values located on the mode

pins are those desired is to construct a circuit like the one shown

in Figure 12. This circuit forces the value located on the Mode

A pin to logic high; regardless if it latched via the RESET or

ERESET pin.

PROGRAMMABLE I/O

MODE A/PFO

RESET

ERESET

1k⍀

ADSP-2189M

Figure 12. Mode A Pin/EZ-ICE Circuit

See the ADSP-2100 Family EZ-Tools data sheet for complete

information on ICE products.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P35

ADSP-2189MKCAZ-300

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Manufacturer:

Analog Devices Inc.

Description:

Digital Signal Processors & Controllers - DSP, DSC 16B 75 MIPS 2.5V 2 Serial Prts Host Prt

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