OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

ADSP-2189MKSTZ-300

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P35
REV. A
ADSP-2189M
–13–
The ICE-Port interface consists of the following ADSP-2189M
pins: EBR, EINT, EE, EBG, ECLK, ERESET, ELIN, EMS,
and ELOUT.
These ADSP-2189M pins must be connected only to the EZ-
ICE connector in the target system. These pins have no function
except during emulation, and do not require pull-up or pull-
down resistors. The traces for these signals between the ADSP-
2189M and the connector must be kept as short as possible, no
longer than three inches.
The following pins are also used by the EZ-ICE: BR, BG,
RESET, and GND.
The EZ-ICE uses the EE (emulator enable) signal to take con-
trol of the ADSP-2189M in the target system. This causes the
processor to use its ERESET, EBR, and EBG pins instead of
the RESET, BR, and BG pins. The BG output is three-stated.
These signals do not need to be jumper-isolated in your system.
The EZ-ICE connects to your target system via a ribbon cable
and a 14-pin female plug. The female plug is plugged onto the
14-pin connector (a pin strip header) on the target board.
Target Board Connector for EZ-ICE Probe
The EZ-ICE connector (a standard pin strip header) is shown in
Figure 13. You must add this connector to your target board
design if you intend to use the EZ-ICE. Be sure to allow enough
room in your system to fit the EZ-ICE probe onto the 14-pin
connector.
12
34
56
78
9
10
11 12
13 14
GND
KEY (NO PIN)
RESET
BR
BG
TOP VIEW
EBG
EBR
ELOUT
EE
EINT
ELIN
ECLK
EMS
ERESET
Figure 13. Target Board Connector for EZ-ICE
The 14-pin, 2-row pin strip header is keyed at the Pin 7 loca-
tion—you must remove Pin 7 from the header. The pins must
be 0.025 inch square and at least 0.20 inch in length. Pin spac-
ing should be 0.1 × 0.1 inches. The pin strip header must have
at least 0.15 inch clearance on all sides to accept the EZ-ICE
probe plug.
Pin strip headers are available from vendors such as 3M,
McKenzie, and Samtec.
Target Memory Interface
For your target system to be compatible with the EZ-ICE emu-
lator, it must comply with the memory interface guidelines listed
below.
PM, DM, BM, IOM, and CM
Design your Program Memory (PM), Data Memory (DM),
Byte Memory (BM), I/O Memory (IOM), and Composite
Memory (CM) external interfaces to comply with worst case
device timing requirements and switching characteristics as
specified in this data sheet. The performance of the EZ-ICE
may approach published worst case specification for some memory
access timing requirements and switching characteristics.
Note: If your target does not meet the worst case chip specifica-
tion for memory access parameters, you may not be able to
emulate your circuitry at the desired CLKIN frequency. De-
pending on the severity of the specification violation, you may
have trouble manufacturing your system as DSP components
statistically vary in switching characteristic and timing require-
ments within published limits.
Restriction: All memory strobe signals on the ADSP-2189M
(RD, WR, PMS, DMS, BMS, CMS, and IOMS) used in your
target system must have 10 kΩ pull-up resistors connected when
the EZ-ICE is being used. The pull-up resistors are necessary
because there are no internal pull-ups to guarantee their state
during prolonged three-state conditions resulting from typical
EZ-ICE debugging sessions. These resistors may be removed at
your option when the EZ-ICE is not being used.
Target System Interface Signals
When the EZ-ICE board is installed, the performance on some
system signals change. Design your system to be compatible
with the following system interface signal changes introduced by
the EZ-ICE board:
• EZ-ICE emulation introduces an 8 ns propagation delay
between your target circuitry and the DSP on the RESET
signal.
• EZ-ICE emulation introduces an 8 ns propagation delay
between your target circuitry and the DSP on the BR signal.
• EZ-ICE emulation ignores RESET and BR when single-
stepping.
• EZ-ICE emulation ignores RESET and BR when in Emula-
tor Space (DSP halted).
• EZ-ICE emulation ignores the state of target BR in certain
modes. As a result, the target system may take control of the
DSP’s external memory bus only if bus grant (BG) is as-
serted by the EZ-ICE board’s DSP.
REV. A
–14–
ADSP-2189M–SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
K Grade B Grade
Parameter Min Max Min Max Unit
V
DDINT
2.37 2.63 2.25 2.75 V
V
DDEXT
2.37 3.6 2.25 3.6 V
V
INPUT
1
V
IL
= –0.3 V
IH
= 3.6 –0.03 3.6 V
T
AMB
0 +70 –40 +85 °C
NOTES
1
The ADSP-2189M is 3.3 V tolerant (always accepts up to 3.6 Volt max V
IH)
, but voltage compliance (on outputs, V
OH
) depends on the input V
DDEXT
; because V
OH
(max) ≈ V
DDEXT
(max). This applies to Bidirectional pins (D0–D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A1–A13, PF0–PF7) and Input Only pins (CLKIN,
RESET, BR, DR0, DR1, PWD).
ELECTRICAL CHARACTERISTICS
K/B Grades
Parameter Test Conditions Min Typ Max Unit
V
IH
, Hi-Level Input Voltage
1, 2
@V
DDINT
= max 1.5 V
V
IH
, Hi-Level CLKIN Voltage @ V
DDINT
= max 2.0 V
V
IL
, Lo-Level Input Voltage
1, 3
@V
DDINT
= min 0.6 V
V
OH
, Hi-Level Output Voltage
1, 4 , 5
@V
DDEXT
= min, I
OH
= –0.5 mA 2.0 V
@V
DDEXT
= 3.0 V, I
OH
= –0.5 mA 2.4 V
@V
DDEXT
= min, I
OH
= –100 µA
6
V
DDEXT
– 0.3 V
V
OL
, Lo-Level Output Voltage
1, 4, 5
@V
DDEXT
= min, I
OL
= 2 mA 0.4 V
I
IH
, Hi-Level Input Current
3
@V
DDINT
= max, V
IN
= 3.6 V 10 µA
I
IL
, Lo-Level Input Current
3
@V
DDINT
= max, V
IN
= 0 V 10 µA
I
OZH
, Three-State Leakage Current
7
@V
DDINT
= max, V
IN
= 3.6 V
8
10 µA
I
OZL
, Three-State Leakage Current
7
@V
DDINT
= max, V
IN
= 0 V
8
10 µA
I
DD
, Supply Current (Idle)
9
@V
DDINT
= 2.5, t
CK
= 15 ns 9 mA
I
DD
, Supply Current (Idle)
9
@V
DDINT
= 2.5, t
CK
= 13.3 ns 10 mA
I
DD
, Supply Current (Dynamic)
10
@V
DDINT
= 2.5, t
CK
= 15 ns
11
,
T
AMB
= +25°C32mA
I
DD
, Supply Current (Dynamic)
10
@V
DDINT
= 2.5, t
CK
= 13.3 ns
11
,
T
AMB
= +25°C36mA
I
DD
, Supply Current (Power-Down)
12, 15
Lowest Power Mode 150 µA
C
I
, Input Pin Capacitance
3, 6, 13
@V
IN
= 2.5 V,
f
IN
= 1.0 MHz,
T
AMB
= +25°C8pF
C
O
, Output Pin Capacitance
6, 7, 12, 14
@V
IN
= 2.5 V,
f
IN
= 1.0 MHz,
T
AMB
= +25°C8pF
NOTES
1
Bidirectional pins: D0–D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A1–A13, PF0–PF7.
2
Input Only pins: RESET, BR, DR0, DR1, PWD.
3
Input Only pins: CLKIN, RESET, BR, DR0, DR1, PWD.
4
Output pins: BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, PWDACK, A0, DT0, DT1, CLKOUT, FL2-0, BGH.
5
Although specified for TTL outputs, all ADSP-2189M outputs are CMOS-compatible and will drive to V
DDEXT
and GND, assuming no dc loads.
6
Guaranteed but not tested.
7
Three-statable pins: A0–A13, D0-D23, PMS, DMS, BMS, IOMS, CMS, RD, WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RFS1, PF0–PF7.
8
0 V on BR.
9
Idle refers to ADSP-2189M state of operation during execution of IDLE instruction. Deasserted pins are driven to either V
DD
or GND.
10
I
DD
measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (types 1, 4, 5, 12, 13, 14), 30% are type 2
and type 6, and 20% are idle instructions.
11
V
IN
= 0 V and 3 V. For typical figures for supply currents, refer to Power Dissipation section.
12
See Chapter 9 of the ADSP-2100 Family User’s Manual, Third Edition for details.
13
Applies to LQFP package type.
14
Output pin capacitance is the capacitive load for any three-stated output pin.
15
V
DDINT
= 2.5 V. T = 25°C.
Specifications subject to change without notice.
REV. A
ADSP-2189M
–15–
TIMING PARAMETERS
GENERAL NOTES
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results for
an individual device, the values given in this data sheet reflect
statistical variations and worst cases. Consequently, you cannot
meaningfully add up parameters to derive longer times.
TIMING NOTES
Switching characteristics specify how the processor changes its
signals. You have no control over this timing—circuitry external
to the processor must be designed for compatibility with these
signal characteristics. Switching characteristics tell you what the
processor will do in a given circumstance. You can also use
switching characteristics to ensure that any timing requirement
of a device connected to the processor (such as memory) is
satisfied.
Timing requirements apply to signals that are controlled by
circuitry external to the processor, such as the data input for a
read operation. Timing requirements guarantee that the proces-
sor operates correctly with other devices.
MEMORY TIMING SPECIFICATIONS
The table below shows common memory device specifications
and the corresponding ADSP-2189M timing parameters, for
your convenience.
Memory Timing
Device Parameter
Specification Parameter Definition
1
Address Setup to t
ASW
A0–A13, xMS Setup before
Write Start WR Low
Address Setup to t
AW
A0–A13, xMS Setup before
Write End WR Deasserted
Address Hold Time t
WRA
A0–A13, xMS Hold before
WR Low
Data Setup Time t
DW
Data Setup before WR
High
Data Hold Time t
DH
Data Hold after WR High
OE to Data Valid t
RDD
RD Low to Data Valid
Address Access Time t
AA
A0–A13, xMS to Data Valid
NOTE
1
xMS = PMS, DMS, BMS, CMS or IOMS.
ABSOLUTE MAXIMUM RATINGS
1
Value
Parameter Min Max
Internal Supply Voltage (V
DDINT
) –0.3 V +3.0 V
External Supply Voltage (V
DDEXT
) –0.3 V +4.6 V
Input Voltage
2
–0.5 V +4.6 V
Output Voltage Swing
3
–0.5 V V
DDEXT
+ 0.5 V
Operating Temperature Range (Ambient) –40°C +85°C
Storage Temperature Range –65°C +150°C
Lead Temperature (5 sec) LQFP +280°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. These are stress ratings only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
Applies to Bidirectional pins (D0–D23, RFS0, RFS1, SCLK0, SCLK1, TFS0,
TFS1, A1–A13, PF0–PF7) and Input only pins (CLKIN, RESET, BR, DR0,
DR1, PWD).
3
Applies to Output pins (BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, PWDACK,
A0, DT0, DT1, CLKOUT, FL2-0, BGH).
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADSP-2189M features proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P35

ADSP-2189MKSTZ-300

Mfr. #:
Buy ADSP-2189MKSTZ-300
Manufacturer:
Analog Devices Inc.
Description:
Digital Signal Processors & Controllers - DSP, DSC 16B 75 MIPS 2.5V 2 Serial Prts Host Prt
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet