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ADSP-2189MKSTZ-300

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P35
REV. A
ADSP-2189M
–19–
TIMING PARAMETERS
Parameter Min Max Unit
Clock Signals and Reset
Timing Requirements:
t
CKI
CLKIN Period 26.6 80 ns
t
CKIL
CLKIN Width Low 13 ns
t
CKIH
CLKIN Width High 13 ns
Switching Characteristics:
t
CKL
CLKOUT Width Low 0.5t
CK
– 2ns
t
CKH
CLKOUT Width High 0.5t
CK
– 2ns
t
CKOH
CLKIN High to CLKOUT High 0 13 ns
Control Signals
Timing Requirements:
t
RSP
RESET Width Low 5t
CK
1
ns
t
MS
Mode Setup before RESET High 2 ns
t
MH
Mode Hold after RESET High 5 ns
NOTE
1
Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal
oscillator start-up time).
t
CKOH
t
CKI
t
CKIH
t
CKIL
t
CKH
t
CKL
t
MH
t
MS
CLKIN
CLKOUT
PF(3:0)
*
RESET
*PF3 IS MODE D, PF2 IS MODE C, PF0 IS MODE A
Figure 22. Clock Signals
REV. A
ADSP-2189M
–20–
Parameter Min Max Unit
Interrupts and Flags
Timing Requirements:
t
IFS
IRQx, FI, or PFx Setup before CLKOUT Low
1, 2, 3, 4
0.25t
CK
+ 10 ns
t
IFH
IRQx, FI, or PFx Hold after CLKOUT High
1, 2, 3, 4
0.25t
CK
ns
Switching Characteristics:
t
FOH
Flag Output Hold after CLKOUT Low
5
0.5t
CK
– 5ns
t
FOD
Flag Output Delay from CLKOUT Low
5
0.5t
CK
+ 4 ns
NOTES
1
If IRQx and FI inputs meet
t
IFS
and t
IFH
setup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be recognized on
the following cycle. (Refer to Interrupt Controller Operation in the Program Control chapter of the ADSP-2100 Family User’s Manual, Third Edition, for further
information on interrupt servicing.)
2
Edge-sensitive interrupts require pulsewidths greater than 10 ns; level-sensitive interrupts must be held low until serviced.
3
IRQx = IRQ0, IRQ1, IRQ2, IRQL0, IRQL1, IRQLE.
4
PFx = PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7.
5
Flag Outputs = PFx, FL0, FL1, FL2, Flag_out4.
t
FOD
t
FOH
t
IFH
t
IFS
CLKOUT
FLAG
OUTPUTS
IRQx
FI
PFx
Figure 23. Interrupts and Flags
REV. A
ADSP-2189M
–21–
Parameter Min Max Unit
Bus Request–Bus Grant
Timing Requirements:
t
BH
BR Hold after CLKOUT High
1
0.25t
CK
+ 2 ns
t
BS
BR Setup before CLKOUT Low
1
0.25t
CK
+ 10 ns
Switching Characteristics:
t
SD
CLKOUT High to xMS, RD, WR Disable 0.25t
CK
+ 8 ns
t
SDB
xMS, RD, WR Disable to BG Low 0 ns
t
SE
BG High to xMS, RD, WR Enable 0 ns
t
SEC
xMS, RD, WR Enable to CLKOUT High 0.25t
CK
– 3ns
t
SDBH
xMS, RD, WR Disable to BGH Low
2
0ns
t
SEH
BGH High to xMS, RD, WR Enable
2
0ns
NOTES
xMS = PMS, DMS, CMS, IOMS, BMS
1
BR is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized on
the following cycle. Refer to the ADSP-2100 Family User’s Manual, Third Edition, for BR/BG cycle relationships.
2
BGH is asserted when the bus is granted and the processor or BDMA requires control of the bus to continue.
CLKOUT
t
SD
t
SDB
t
SE
t
SEC
t
SDBH
t
SEH
t
BS
BR
t
BH
CLKOUT
PMS, DMS
BMS, RD
WR
BG
BGH
Figure 24. Bus Request–Bus Grant
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P35

ADSP-2189MKSTZ-300

Mfr. #:
Buy ADSP-2189MKSTZ-300
Manufacturer:
Analog Devices Inc.
Description:
Digital Signal Processors & Controllers - DSP, DSC 16B 75 MIPS 2.5V 2 Serial Prts Host Prt
Lifecycle:
New from this manufacturer.
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