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9UMS9633BKLF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22
ICS9UMS9633B
IDT
TM
/ICS
TM
Ultra Mobile PC/Mobile Internet Device 1423—01/20/09
Advance Information
ULTRA MOBILE PC/MOBILE INTERNET DEVICE
1
Recommended Application: Features/Benefits:
Poulsbo Based Ultra-Mobile PC (UMPC)
• Supports Dothan ULV CPUs with 67 to 167
MHz CPU outputs
• Dedicated TEST/SEL and TEST/MODE pins
saves isolation resistors on pins
• CPU STOP# input for power manangment
• Fully integrated Vreg
• Integrated series resistors on differential
outputs
• 1.5V VDD IO operation, 3.3V VDD core and
REF supply pin for REF
• Industrial Temperature (-40 to +85C) version
available
Output Features:
• 3 - CPU low power differential push-pull pairss
• 3 - SRC low power differential push-pull pairs
• 1 - LCD100 SSCD low power differential
push-pull pair
• 1 - DOT96 low power differential push-pull
pair
• 1 - REF, 14.31818MHz, 3.3V SE output
SSOP Pin Configuration
REF 1 48 VDDREF_3.3
GNDREF 2 47 X1
VDDCORE_3.3 3 46 X2
FSC_L 4 45 CLKPWRGD#/PD_3.3
TEST_MODE 5 44 CPU_STOP#
TEST_SEL 6 43 CPUT0_LPR
SCLK 7 42 CPUC0_LPR
SDATA 8 41 VDDIO_1.5
VDDCORE_3.3 9 40 GNDCPU
VDDIO_1.5 10 39 CPUT1_LPR
DOT96C_LPR 11 38 CPUC1_LPR
DOT96T_LPR 12 37 VDDCORE_3.3
GNDDOT 13 36 VDDIO_1.5
GNDLCD 14 35 GNDCPU
LCD100C_LPR 15 34 CPUT2_LPR
LCD100T_LPR 16 33 CPUC2_LPR
VDDIO_1.5 17 32 FSB_L
VDDCORE_3.3 18 31 *CR#2
*CR#0 19 30 SRCT2_LPR
GNDSRC 20 29 SRCC2_LPR
SRCC0_LPR 21 28 GNDSRC
SRCT0_LPR 22 27 SRCT1_LPR
*CR#1 23 26 SRCC1_LPR
VDDCORE_3.3 24
25 VDDIO_1.5
9UMS9633
* indicates inputs with internal pull up of ~10Kohm to 3.3V
48 SSOP Package
IDT
TM
/ICS
TM
Ultra Mobile PC/Mobile Internet Device 1423—01/20/09
ICS9UMS9633B
ULTRA MOBILE PC/MOBILE INTERNET DEVICE
2
Advance Information
SSOP Pin Description
PIN # PIN NAME TYPE DESCRIPTION
1 REF OUT 14.318 MHz reference clock.
2 GNDREF PWR Ground pin for the REF outputs.
3 VDDCORE_3.3 PWR 3.3V power for the PLL core
4FSC_L IN
Low threshold input for CPU frequency selection. Refer to input electrical
characteristics for Vil_FS and Vih_FS values.
5TEST_MODE IN
TEST_MODE is a real time input to select between Hi-Z and REF/N divider mode
while in test mode. Refer to Test Clarification Table.
6 TEST_SEL IN
TEST_SEL: latched input to select TEST MODE
1 = All outputs are tri-stated for test
0 = All outputs behave normally.
7 SCLK IN Clock pin of SMBus circuitry, 5V tolerant.
8 SDATA I/O Data pin for SMBus circuitr
y
, 3.3V tolerant.
9 VDDCORE_3.3 PWR 3.3V power for the PLL core
10 VDDIO_1.5 PWR Power supply for low power differential outputs, nominal 1.5V.
11 DOT96C_LPR OUT
Complement clock of low power differential pair for 96.00MHz DOT clock. No 50ohm
resistor to GND needed. No Rs needed.
12 DOT96T_LPR OUT
True clock of low power differential pair for 96.00MHz DOT clock. No 50ohm resistor
to GND needed. No Rs needed.
13 GNDDOT PWR Ground pin for DOT clock output
14 GNDLCD PWR Ground pin for LCD clock output
15 LCD100C_LPR OUT
Complement clock of low power differential pair for LCD100 SS clock. No 50ohm
resistor to GND needed. No Rs needed.
16 LCD100T_LPR OUT
True clock of low power differential pair for LCD100 SS clock. No 50ohm resistor to
GND needed. No Rs needed.
17 VDDIO_1.5 PWR Power suppl
y
for low power differential outputs, nominal 1.5V.
18 VDDCORE_3.3 PWR 3.3V power for the PLL core
19 *CR#0 IN Clock request for SRC0, 0 = enable, 1 = disable
20 GNDSRC PWR Ground pin for the SRC outputs
21 SRCC0_LPR OUT
Complementary clock of differential 0.8V push-pull SRC output with integrated 33ohm
series resistor. No 50ohm resistor to GND needed.
22 SRCT0_LPR OUT
True clock of differential 0.8V push-pull SRC output with integrated 33ohm series
resistor. No 50ohm resistor to GND needed.
23 *CR#1 IN Clock request for SRC1, 0 = enable, 1 = disable
24 VDDCORE_3.3 PWR 3.3V power for the PLL core
IDT
TM
/ICS
TM
Ultra Mobile PC/Mobile Internet Device 1423—01/20/09
ICS9UMS9633B
ULTRA MOBILE PC/MOBILE INTERNET DEVICE
3
Advance Information
SSOP Pin Description (continued)
PIN # PIN NAME TYPE DESCRIPTION
25 VDDIO_1.5 PWR Power supply for low power differential outputs, nominal 1.5V.
26 SRCC1_LPR OUT
Complementary clock of differential 0.8V push-pull SRC output with integrated 33ohm
series resistor. No 50ohm resistor to GND needed.
27 SRCT1_LPR OUT
True clock of differential 0.8V push-pull SRC output with integrated 33ohm series
resistor. No 50ohm resistor to GND needed.
28 GNDSRC PWR Ground pin for the SRC outputs
29 SRCC2_LPR OUT
Complementary clock of differential 0.8V push-pull SRC output with integrated 33ohm
series resistor. No 50ohm resistor to GND needed.
30 SRCT2_LPR OUT
True clock of differential 0.8V push-pull SRC output with integrated 33ohm series
resistor. No 50ohm resistor to GND needed.
31 *CR#2 IN Clock request for SRC2, 0 = enable, 1 = disable
32 FSB_L IN
Low threshold input for CPU frequency selection. Refer to input electrical
characteristics for Vil_FS and Vih_FS values.
33 CPUC2_LPR OUT
Complementary clock of differential pair 0.8V push-pull CPU outputs with integrated
33ohm series resistor. No 50 ohm resistor to GND needed.
34 CPUT2_LPR OUT
True clock of differential pair 0.8V push-pull CPU outputs with integrated 33ohm
series resistor. No 50 ohm resistor to GND needed.
35 GNDCPU PWR Ground pin for the CPU outputs
36 VDDIO_1.5 PWR Power suppl
y
for low power differential outputs, nominal 1.5V.
37 VDDCORE_3.3 PWR 3.3V power for the PLL core
38 CPUC1_LPR OUT
Complementary clock of differential pair 0.8V push-pull CPU outputs with integrated
33ohm series resistor. No 50 ohm resistor to GND needed.
39 CPUT1_LPR OUT
True clock of differential pair 0.8V push-pull CPU outputs with integrated 33ohm
series resistor. No 50 ohm resistor to GND needed.
40 GNDCPU PWR Ground pin for the CPU outputs
41 VDDIO_1.5 PWR Power supply for low power differential outputs, nominal 1.5V.
42 CPUC0_LPR OUT
Complementary clock of differential pair 0.8V push-pull CPU outputs with integrated
33ohm series resistor. No 50 ohm resistor to GND needed.
43 CPUT0_LPR OUT
True clock of differential pair 0.8V push-pull CPU outputs with integrated 33ohm
series resistor. No 50 ohm resistor to GND needed.
44 CPU_STOP# IN Stops all CPU clocks, except those set to be free runnin
g
clocks
45 CLKPWRGD#/PD_3.3 IN
This 3.3V LVTTL input is a level sensitive strobe used to determine when latch inputs
are valid and are ready to be sampled. This is an active low input. / Asynchronous
active high input pin used to place the device into a power down state.
46 X2 OUT Crystal output, Nominally 14.318MHz
47 X1 IN Crystal input, Nominally 14.318MHz.
48 VDDREF_3.3 PWR Power pin for the XTAL and REF clocks, nominal 3.3V
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22

9UMS9633BKLF

Mfr. #:
Buy 9UMS9633BKLF
Manufacturer:
IDT
Description:
Clock Generators & Support Products PC MAIN CLOCK - LOW POWER - ATOM 3.3V
Lifecycle:
New from this manufacturer.
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