9UMS9633BKLF Datasheet 9UMS9633BKLF, 9UMS9633BKLFT | P13-P15

IDT

/ICS

Ultra Mobile PC/Mobile Internet Device 1423—01/20/09

ICS9UMS9633B

ULTRA MOBILE PC/MOBILE INTERNET DEVICE

Advance Information

Byte 0 PLL & Divider Enable Register

Bit(s) Pin # Name Description Type 0 1 Default

7 - PLL1 Enable

This bit controls whether the PLL driving the CPU

and SRC clocks is enabled or not.

RW 0 = Disabled 1 = Enabled 1

6 - PLL2 Enable

This bit controls whether the PLL driving the DOT

and clock is enabled or not.

RW 0 = Disabled 1 = Enabled 1

5 - PLL3 Enable

This bit controls whether the PLL driving the LCD

clock is enabled or not.

RW 0 = Disabled 1 = Enabled 1

4- 0

3 - CPU Divider Enable

This bit controls whether the CPU output divider is

enabled or not.

NOTE:

This bit should be automatically set to ‘0’ if

bit 7 is set to ‘0’.

RW 0 = Disabled 1 = Enabled 1

SRC Output Divider

Enable

This bit controls whether the SRC output divider is

enabled or not.

NOTE: This bit should be automatically set to ‘0’ if

bit 7 is set to ‘0’.

RW 0 = Disabled 1 = Enabled 1

LCD Output Divider

Enable

This bit controls whether the LCD output divider is

enabled or not.

NOTE:

This bit should be automatically set to ‘0’ if

bit 5 is set to ‘0’.

RW 0 = Disabled 1 = Enabled 1

DOT Output Divider

Enable

This bit controls whether the DOT output divider is

enabled or not.

NOTE:

This bit should be automatically set to ‘0’ if

bit 6 is set to ‘0’.

RW 0 = Disabled 1 = Enabled 1

Byte 1 PLL SS Enable/Control Register

Bit(s) Pin # Name Description Type 0 1 Default

7 PLL1 SS Enable

This bit controls whether PLL1 has spread enabled

or not. Spread spectrum for PLL1 is set at -0.5%

down-spread. Note that PLL1 drives the CPU and

SRC clocks.

RW 0 = Disabled 1 = Enabled 1

6 PLL3 SS Enable

This bit controls whether PLL3 has spread enabled

or not. Note that PLL3 drives the SSC clock, and

that the spread spectrum amount is set in bits 3-5.

RW 0 = Disabled 1 = Enabled 1

5 0

4 0

3 0

2 0

1 0

0 0

Reserved

See Table 2: LCD Spread

Select Table

PLL3 FS Select

These 3 bits select the frequency of PLL3 and the

SSC clock when Byte 1 Bit 6 (PLL3 Spread

Spectrum Enable) is set.

IDT

/ICS

Ultra Mobile PC/Mobile Internet Device 1423—01/20/09

ICS9UMS9633B

ULTRA MOBILE PC/MOBILE INTERNET DEVICE

Advance Information

Byte 2 Output Enable Register

Bit(s) Pin # Name Description Type 0 1 Default

7 CPU0 Enable

This bit controls whether the CPU[0] output buffer

is enabled or not.

RW 0 = Disabled 1 = Enabled 1

6 CPU1 Enable

This bit controls whether the CPU[1] output buffer

is enabled or not.

RW 0 = Disabled 1 = Enabled 1

5 CPU2 Enable

This bit controls whether the CPU[2] output buffer

is enabled or not.

RW 0 = Disabled 1 = Enabled 1

4 SRC0 Enable

This bit controls whether the SRC[0] output buffer

is enabled or not.

RW 0 = Disabled 1 = Enabled 1

3 SRC1 Enable

This bit controls whether the SRC[1] output buffer

is enabled or not.

RW 0 = Disabled 1 = Enabled 1

2 SRC2 Enable

This bit controls whether the SRC[2] output buffer

is enabled or not.

RW 0 = Disabled 1 = Enabled 1

1 DOT Enable

This bit controls whether the DOT output buffer is

enabled or not.

RW 0 = Disabled 1 = Enabled 1

0 LCD100 Enable

This bit controls whether the LCD output buffer is

enabled or not.

RW 0 = Disabled 1 = Enabled 1

Byte 3 Output Control Register

Bit(s) Pin # Name Description Type 0 1 Default

7 0

6 0

5 REF Enable

This bit controls whether the REF output buffer is

enabled or not.

RW 0 = Disabled 1 = Enabled 1

2 CPU0 Stop Enable

This bit controls whether the CPU[0] output buffer

is free-running or stoppable. If it is set to stoppable

the CPU[0] output buffer will be disabled with the

assertion of CPU_STP#.

RW Free Running Stoppable 0

1 CPU1 Stop Enable

This bit controls whether the CPU[1] output buffer

is free-running or stoppable. If it is set to stoppable

the CPU[1] output buffer will be disabled with the

assertion of CPU_STP#.

RW Free Running Stoppable 0

0 CPU2 Stop Enable

This bit controls whether the CPU[2] output buffer

is free-running or stoppable. If it is set to stoppable

the CPU[2] output buffer will be disabled with the

assertion of CPU_STP#.

RW Free Running Stoppable 0

10REF Slew

00 = Slow Edge Rate

01 = Medium Edge Rate

10 = Fast Edge Rate

11 = Reserved

RWThese bits control the edge rate of the REF clock.

Reserved

IDT

/ICS

Ultra Mobile PC/Mobile Internet Device 1423—01/20/09

ICS9UMS9633B

ULTRA MOBILE PC/MOBILE INTERNET DEVICE

Advance Information

Byte 4

PU PLL N Register

Bit(s) Pin # Name Control Function Type 0 1 Default

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

CPU N Div8 N Divider Prog bit 8 RW 0

Byte 5

PU PLL/N Register

Bit(s) Pin # Name Control Function Type 0 1 Default

Bit 7

CPU N Div7 RW X

Bit 6

CPU N Div6 RW X

Bit 5

CPU N Div5 RW X

Bit 4

CPU N Div4 RW X

Bit 3

CPU N Div3 RW X

Bit 2

CPU N Div2 RW X

Bit 1

CPU N Div1 RW X

Bit 0

CPU N Div0 RW X

Byte 6 Reserved

Bit(s) Pin # Name Control Function Type 0 1 Default

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Byte 7 Reserved

Bit(s) Pin # Name Control Function Type 0 1 Default

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reserved

See Table 3: CPU N-step Programming

Default depends on latched

input frequency.

Default for CPU = 166 is 7Dh.

Default for all other frequencies

is 64h.

Reserved

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P22

9UMS9633BKLF

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Manufacturer:

IDT

Description:

Clock Generators & Support Products PC MAIN CLOCK - LOW POWER - ATOM 3.3V

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9UMS9633BKLF

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