LH52256C/CH
CMOS 256K (32K × 8) Static RAM
FEATURES
•• 32,768 × 8 bit organization
•• Access time: 70 ns (MAX.)
•• Supply current:
Operating: 45 mA (MAX.)
10 mA (MAX.) (t
RC
, t
WC
= 1 µs)
Standby: 40 µA (MAX.)
•• Data retention current: 1.0 µA (MAX.)
(V
CCDR
= 3 V, T
A
= 25°C)
•• Wide operating voltage range:
4.5 V ± 5.5 V
•• Operating temperature:
Commerical temperature 0°C to +70°C
Industrial temperature -40° to +85°C
•• Fully-static operation
•• Three-state outputs
•• Not designed or rated as radiation
hardened
•• Package:
28-pin, 600-mil DIP
28-pin, 450-mil SOP
28-pin, 300-mil SK-DIP
28-pin, 8 × 3 mm
2
TSOP (Type I)
•• N-type bulk silicon
DESCRIPTION
The LH52256C is a Static RAM organized as
32,768 × 8 bits which provides low-power standby
mode. It is fabricated using silicon-gate CMOS process
technology.
PIN CONNECTIONS
52256C-1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
A
14
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
WE
A
9
A
11
OE
A
10
I/O
6
I/O
5
GND
I/O
8
I/O
7
CE
A
13
A
8
I/O
1
I/O
2
I/O
3
I/O
4
28-PIN DIP
28-PIN SK-DIP
28-PIN SOP
TOP VIEW
Figure 1. Pin Connections
2
3
4
5
6
9
10
7
8
A
11
11
1
28
27
26
25
22
21
24
23
20
19
A
10
28-PIN TSOP (Type I)
12
13
14
17
16
18
15
OE
A
8
A
9
A
13
WE
A
12
A
14
I/O
3
I/O
2
A
1
I/O
8
CE
I/O
6
I/O
7
GND
I/O
5
I/O
4
I/O
1
A
0
52256C-8
V
CC
A
7
A
6
A
5
A
4
A
3
A
2
NOTE: Reverse bend available on request.
Figure 2. TSOP (Type I) Pin Connections
1
