LH52256C-70LL

DC ELECTRICAL CHARACTERISTICS (T
A
= 0°C to +70°C, V
CC
= 4.5 V to 5.5 V)
PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNIT
Input leakage
current
I
LI
V
IN
= 0 V to V
CC
–1.0
1.0 µA
Output leakage
current
I
LO
CE = V
IH
or OE = V
IH
V
I/O
= 0 V to V
CC
–1.0
1.0
µA
Operating supply
current
I
CC
Minimum cycle, V
IN
= V
IL
or V
IH
I
I/O
= 0 mA, CE = V
IL
25 45.0
mA
I
CC1
t
RC
, t
WC
= 1 µs, V
IN
= V
IL
or V
IH
,
I
I/O
= 0 mA, CE = V
IL

10.0
Standby current
I
SB
CE V
CC
– 0.2 V
0.6 40.0
µA
I
SB1
CE = V
IH

3.0 mA
Output voltage
V
OL
I
OL
= 2.1 mA

0.4
V
V
OH
I
OH
= -1.0 mA 2.4

NOTE:
Typical values at V
CC
= 5.0 V, T
A
= 25°C
AC ELECTRICAL CHARACTERISTICS
AC Test Conditions
PARAMETER MODE NOTE
Input pulse level
0.6 V to 2.4 V
Input rise and fall time
10 ns
Input and output timing Ref. level 1.5 V
Output load
1 TTL + C
L
(100 pF) 1
NOTE:
1. Including scope and jig capacitance.
READ CYCLE (T
A
= 0°C to +70°C, V
CC
= 4.5 V to 5.5 V)
PARAMETER SYMBOL MIN. MAX. UNIT NOTE
Read cycle time t
RC
70
ns
Address access time t
AA
70 ns
CE access time t
ACE
70 ns
Output enable to output valid
t
OE
35 ns
Output hold from address change t
OH
10
ns
CE Low to output active t
LZ
10
ns 1
OE Low to output active t
OLZ
5
ns 1
CE High to output in High impedance t
HZ
030ns1
OE High to output in High impedance t
OHZ
030ns1
NOTES:
1.
Active output to high-impedance and high-impedance to output active tests specified for a ±200 mV
transition from steady state levels into the test load.
LH52256C/CH CMOS 256K (32K × 8) Static RAM
4
WRITE CYCLE (T
A
= 0°C to +70°C, V
CC
= 4.5 V to 5.5 V)
PARAMETER SYMBOL MIN. MAX. UNIT NOTE
Write cycle time t
WC
70
ns
CE Low to end of write t
CW
45
ns
Address valid to end of write
t
AW
45
ns
Address setup time t
AS
0
ns
Write pulse width t
WP
35
ns
Write recovery time t
WR
0
ns
Input data setup time
t
DW
30
ns
Input data hold time t
DH
0
ns
WE High to output active t
OW
5
ns 1
WE Low to output in High
impedance
t
WZ
030ns1
OE High to output in High
impedance
t
OHZ
030ns1
NOTE:
1.
Active output to high-impedance and high-impedance to output active tests specified for a ±200 mV
transition from steady state levels into the test load.
CAPACITANCE (T
A
= 25°C, f = 1MHz)
PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNIT NOTE
Input capacitance C
IN
V
IN
= 0 V

7pF1
I/O capacitance
C
I/O
V
I/O
= 0 V

10 pF 1
NOTE:
1. This parameter is sampled and not production tested.
DATA RETENTION CHARACTERISTICS (T
A
= 0°C to +70°C)
PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNIT NOTE
Data retention supply voltage
V
CCDR
CE V
CCDR
– 0.2 V 2.0
5.5 V
Data retention supply current I
CCDR
V
CCDR
= 3.0 V
CE V
CCDR
– 0.2 V
T
A
= 25°C
0.3 1.0
µA
TA = 40°C

3.0
15
Chip enable setup time t
CDR
0

ns
Chip enable hold time t
R
t
RC

ns 1
NOTE:
1. t
RC
= Read cycle time.
2.
Typical values at T
A
= 25°C
CMOS 256K (32K × 8) Static RAM LH52256C/CH
5
D
OUT
DATA VALID
t
RC
t
AA
t
ACE
t
LZ
t
OLZ
t
OH
t
OHZ
t
HZ
52256C-3
ADDRESS
t
OE
OE
CE
NOTE: WE is HIGH for Read Cycle.
Figure 4. Read Cycle
LH52256C/CH CMOS 256K (32K × 8) Static RAM
6

LH52256C-70LL

Mfr. #:
Manufacturer:
Sharp Microelectronics
Description:
IC SRAM 256K PARALLEL 28DIP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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