DATA VALID
t
DH
t
DW
WE
D
IN
t
CW
ADDRESS
t
WC
52256C-5
t
WR
t
AW
CE
t
AS
t
WZ
t
WP
(NOTE 2
)
(NOTE 4)
(NOTE 3)
D
OUT
(NOTE 6)
(NOTE 1)
t
WR
t
OW
(NOTE 7)
(NOTE 5)
(NOTE 4)
1. A write occurs during the overlap of a LOW CE, and a LOW WE.
A write begins at the latest transition among CE going LOW, and
WE going LOW. A write ends at the earliest transition among CE
going HIGH, and WE going HIGH. t
WP
is measured from the beginning
of write to the end of write.
2. t
CW
is measured from the later of CE going LOW to the end of write.
3. t
AS
is measured from the address valid to the beginning of write.
4. t
WR
is measured from the end of write to the address change.
5. During this period, I/O pins are in the output state, therefore the input
signals of opposite phase to the outputs must not be applied.
6. If CE goes LOW simultaneously with WE going LOW or after WE going
LOW, the outputs remain in high impedance state.
7. If CE goes HIGH simulaneously with WE going HIGH or before WE
going HIGH, the outputs remain in high impedance state.
NOTES:
Figure 6. Write Cycle (OE Low Fixed)
t
CDR
V
CC
4.5 V
2.2 V
V
CCDR
0 V
CE
CE ≥ V
CCDR
- 0.2 V
DATA RETENTION MODE
t
R
52256C-6
CE
CONTROL
Data Retention Timing Chart
CE Controlled
LH52256C/CH CMOS 256K (32K × 8) Static RAM
8
