1. General description
The 74HC4020-Q100; 74HCT4020-Q100 are 14-stage binary ripple counters with a clock
input (CP
), an overriding asynchronous master reset input (MR) and 12 buffered parallel
outputs (Q0, and Q3 to Q13). The counter advances on the HIGH-to-LOW transition of
CP
. A HIGH on MR clears all counter stages and forces all outputs LOW, independent of
the state of CP
. Each counter stage is a static toggle flip-flop.. Inputs include clamp
diodes. This enables the use of current limiting resistors to interface inputs to voltages in
excess of V
CC
.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Input levels:
For 74HC4020-Q100: CMOS level
For 74HCT4020-Q100: TTL level
Complies with JEDEC standard no. 7A
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
Multiple package options
3. Applications
Frequency dividing circuits
Time delay circuits
Control counters
74HC4020-Q100;
74HCT4020-Q100
14-stage binary ripple counter
Rev. 1 — 23 May 2013 Product data sheet
