74HC_HCT4020_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 23 May 2013 9 of 18
NXP Semiconductors
74HC4020-Q100; 74HCT4020-Q100
14-stage binary ripple counter
[1] t
pd
is the same as t
PHL
and t
PLH
.
[2] t
t
is the same as t
THL
and t
TLH
.
[3] C
PD
is used to determine the dynamic power dissipation (P
D
in W).
P
D
= C
PD
V
CC
2
f
i
+ (C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
(C
L
V
CC
2
f
o
) = sum of outputs;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V.
12. Waveforms
f
max
maximum
frequency
see Figure 8
V
CC
= 4.5 V; C
L
=50pF 25 47 - 20 - 17 - MHz
V
CC
= 5.0 V; C
L
=15pF - 52 - - - - - MHz
C
PD
power
dissipation
capacitance
[3]
-20- - - - - pF
Table 7. Dynamic characteristics
…continued
GND (ground = 0 V); C
L
= 50 pF unless otherwise specified; for test circuit, see Figure 10
Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit
Min Typ Max Min Max Min Max
Measurement points are given in Table 8.
V
OL
and V
OH
are typical voltage output levels that occur with the output load.
Fig 8. Clock timing, propagation delays, pulse widths and measurement points
MR input
90 % 90 %
10 % 10 %
CP input
Q0 or Qn
output
t
W
t
PHL
1/f
max
t
rec
V
M
V
I
V
I
V
M
001aad590
t
PLH
t
W
t
TLH
t
THL
t
PHL
V
M
