74HC_HCT4020_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 23 May 2013 3 of 18
NXP Semiconductors
74HC4020-Q100; 74HCT4020-Q100
14-stage binary ripple counter
6. Pinning information
6.1 Pinning
Fig 4. Logic diagram
001aal204
FF
1
RD
Q
CP
MR
Q
T
FF
2
RD
Q
Q
T
FF
3
RD
Q
Q
T
FF
4
RD
Q
Q
T
FF
6
RD
Q0 Q3 Q13
Q
Q
T
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to V
CC
.
Fig 5. Pin configuration SO16 and TSSOP16 Fig 6. Pin configuration DHVQFN16
+&4
4 9
&&
4 4
4 4
4
4
4
4
4
05
4
&3
*1' 4
DDD
DDD
9
&&

+&4
+&74
4 &3
4 05
4 4
4 4
4 4
4 4
*1'
4
4
9
&&
7UDQVSDUHQWWRSYLHZ







WHUPLQDO
LQGH[DUHD
74HC_HCT4020_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 23 May 2013 4 of 18
NXP Semiconductors
74HC4020-Q100; 74HCT4020-Q100
14-stage binary ripple counter
6.2 Pin description
7. Functional description
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; = LOW-to-HIGH clock transition; = HIGH-to-LOW clock transition.
7.1 Timing diagram
Table 2. Pin description
Symbol Pin Description
Q0, Q3 to Q13 9, 7, 5, 4, 6, 13, 12, 14, 15, 1, 2, 3 output
GND 8 ground (0 V)
CP
10 clock input (HIGH-to-LOW, edge-triggered)
MR 11 master reset input (active HIGH)
V
CC
16 positive supply voltage
Table 3. Function table
Input Output
CP MR Q0, Q3 to Q13
L no change
L count
XHL
Fig 7. Timing diagram
001aal207
12 4
8
16 32 64 128 256 512 1024 2048 4096
CP input
MR input
Q0
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
8192 16384
Q12
Q13
74HC_HCT4020_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 23 May 2013 5 of 18
NXP Semiconductors
74HC4020-Q100; 74HCT4020-Q100
14-stage binary ripple counter
8. Limiting values
[1] For SO16 package: P
tot
derates linearly with 8 mW/K above 70 C.
For TSSOP16 package: P
tot
derates linearly with 5.5 mW/K above 60 C.
For DHVQFN16 package: P
tot
derates linearly with 4.5 mW/K above 60 C.
9. Recommended operating conditions
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
V
CC
supply voltage 0.5 +7 V
I
IK
input clamping current V
I
< 0.5 V or V
I
> V
CC
+0.5V - 20 mA
I
OK
output clamping current V
I
< 0.5 V or V
I
> V
CC
+0.5 V - 20 mA
I
O
output current 0.5 V < V
O
< V
CC
+ 0.5 V - 25 mA
I
CC
supply current - 50 mA
I
GND
ground current - 50 mA
T
stg
storage temperature 65 +150 C
P
tot
total power dissipation T
amb
= 40 C to +125 C
[1]
-500mW
Table 5. Recommended operating conditions
Symbol Parameter Conditions 74HC4020-Q100 74HCT4020-Q100 Unit
Min Typ Max Min Typ Max
V
CC
supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V
V
I
input voltage 0 - V
CC
0-V
CC
V
V
O
output voltage 0 - V
CC
0-V
CC
V
t/V input transition rise and
fall rate
except for
Schmitt trigger inputs
V
CC
= 2.0 V - - 625 - - - ns/V
V
CC
= 4.5 V - 1.67 139 - 1.67 139 ns/V
V
CC
= 6.0 V - - 83 - - - ns/V
T
amb
ambient temperature 40 +25 +125 40 +25 +125 C

74HCT4020BQ-Q100X

Mfr. #:
Manufacturer:
Nexperia
Description:
Counter ICs 14-stage binary ripple counter
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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