IDT71V424L15PH

SEPTEMBER 2013
DSC-3622/10
1
©2013 Integrated Device Technology, Inc.
Features
512K x 8 advanced high-speed CMOS Static RAM
JEDEC Center Power / GND pinout for reduced noise
Equal access and cycle times
Commercial and Industrial: 10/12/15ns
Single 3.3V power supply
One Chip Select plus one Output Enable pin
Bidirectional data inputs and outputs directly
TTL-compatible
Low power consumption via chip deselect
Available in 36-pin, 400 mil plastic SOJ package and
44-pin, 400 mil TSOP.
Functional Block Diagram
Description
The IDT71V424 is a 4,194,304-bit high-speed Static RAM organized
as 512K x 8. It is fabricated using high-perfomance, high-reliability CMOS
technology. This state-of-the-art technology, combined with innovative
circuit design techniques, provides a cost-effective solution for high-speed
memory needs.
The IDT71V424 has an output enable pin which operates as fast as
5ns, with address access times as fast as 10ns. All bidirectional inputs and
outputs of the IDT71V424 are TTL-compatible and operation is from a
single 3.3V supply. Fully static asynchronous circuitry is used, requiring
no clocks or refresh for operation.
The IDT71V424 is packaged in a 36-pin, 400 mil Plastic SOJ and 44-
pin, 400 mil TSOP.
ADDRESS
DECODER
4,194,304-BIT
MEMORY ARRAY
I/O CONTROL
A
0
A
18
8
8
I/O
0
-I/O
7
8
CONTROL
LOGIC
WE
OE
CS
3622 drw 01
3.3V CMOS Static RAM
4 Meg (512K x 8-Bit)
IDT71V424S
IDT71V424L
6.422
IDT71V424S, IDT71V424L, 3.3V CMOS Static RAM
4 Meg (512K x 8-bit) Commercial and Industrial Temperature Ranges
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
A5
NC
NC
A9
A8
A7
WE
I/03
I/02
V
SS
V
DD
I/01
I/00
CS
A2
A1
A0
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
NC
A15
OE
I/07
I/06
V
SS
V
DD
I/05
I/04
A14
A13
A11
A10
NC
NC
NC
NC
A12
SO44-2
3622 drw 11
NC
NC
A3
A4
A6
A16
A17
A18
A0
A1
A2
A3
CS
I/O 0
V
DD
V
SS
I/O 2
WE
A4
A5
A6
A7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
NC
A18
A17
A16
OE
I/O 7
I/O 6
V
SS
V
DD
I/O 5
A14
A13
A12
A11
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
SO36-1
17
18
19
20
I/O 1
I/O 3 I/O 4
NC
A8
A9
A10
A15
3622 drw 02
SOJ
Top View
Pin Configuration
Truth Table
(1,2)
Capacitance
(TA = +25°C, f = 1.0MHz, SOJ package)
Pin Configuration
TSOP
Top View
A
0
– A
18
Address Inputs Input
CS
Chip Select Input
WE
Write Enable Input
OE
Output Enable Input
I/O
0
- I/O
7
Data Input/Output I/O
V
DD
3.3V Power Power
V
SS
Ground Gnd
3622 tbl 02
Pin Description
Symbol Parameter
(1)
Conditions Max. Unit
C
IN
Input Capacitance V
IN
= 3dV 7 pF
C
I/O
I/O Capacitance V
OUT
= 3dV 8 pF
3622 tbl 03
NOTE:
1. This parameter is guaranteed by device characterization, but not production
tested.
CS OE WE I/O Function
LLHDATA
OUT Read Data
LXLDATA
IN Write Data
L H H High-Z Output Disabled
H X X High-Z Deselected - Standby (I
SB)
V
HC
(3)
X X High-Z Deselected - Standby (ISB1)
3622 tbl 01
NOTES:
1. H = VIH, L = VIL, x = Don't care.
2. VLC = 0.2V, VHC = VDD -0.2V.
3. Other inputs VHC or VLC.
6.42
3
IDT71V424S, IDT71V424L, 3.3V CMOS Static RAM
4 Meg (512K x 8-bit) Commercial and Industrial Temperature Ranges
Absolute Maximum Ratings
(1)
Recommended Operating
Temperature and Supply Voltage
Recommended DC Operating
Conditions
DC Electrical Characteristics
(VDD = Min. to Max., Commercial and Industrial Temperature Ranges)
DC Electrical Characteristics
(1, 2, 3)
(VDD = Min. to Max., VLC = 0.2V, VHC = VDD – 0.2V)
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.
NOTES:
1. VIH (max.) = VDD+2V for pulse width less than 5ns, once per cycle.
2. VIL (min.) = –2V for pulse width less than 5ns, once per cycle.
NOTES:
1. All values are maximum guaranteed values.
2. All inputs switch between 0.2V (Low) and VDD - 0.2V (High).
3. Power specifications are preliminary.
4. fMAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing.
Symbol Rating Value Unit
V
DD
Supply Voltage Relative to
V
SS
-0.5 to +4.6 V
V
IN
, V
OUT
Terminal Voltage Relative
to V
SS
-0.5 to V
DD
+0.5 V
T
BIAS
Temperature Under Bias -55 to +125
o
C
T
STG
Storage Temperature -55 to +125
o
C
P
T
Power Dissipation 1 W
I
OUT
DC Output Current 50 mA
3622 tbl 04
Symbol Parameter Min. Typ. Max. Unit
V
DD
Supply Voltage 3.0 3.3 3.6 V
V
SS
Ground 0 0 0 V
V
IH
Input High Voltage 2.0
____
V
DD
+0.3
(1)
V
V
IL
Input Low Voltage -0.3
(2)
____
0.8 V
3622 tbl 06
Grade Temperature V
SS
V
DD
Commercial C to +70°C 0V See Below
Industrial –40°C to +85°C 0V See Below
3622 tbl 05
Symbol Parameter Test Condition
IDT71V424
Min. Max. Unit
|I
LI| Input Leakage Current VDD = Max., VIN = VSS to VDD
___
A
|I
LO| Output Leakage Current VDD = Max., CS = VIH, VOUT = VSS to VDD
___
A
V
OL Output Low Voltage IOL = 8mA, VDD = Min.
___
0.4 V
V
OH Output High Voltage IOH = -4mA, VDD = Min. 2.4
___
V
3622 tbl 07
Symbol Parameter
71V424S/L 10 71V424S/L 12 71V424S/L 15
Unit
Com'l. Ind. Com'l. Ind. Com'l. Ind.
I
CC
Dynamic Operating Current
CS <
V
LC
, Outputs Open, V
DD
= Max., f = f
MAX
(4)
S 180 180 170 170 160 160 mA
L 165 165 155 155 145 145 mA
I
SB
Dynamic Standby Power Supply Current
CS >
V
HC
, Outputs Open, V
DD
= Max., f = f
MAX
(4)
S606055 555050mA
L555550 504545mA
I
SB1
Full Standby Power Supply Current (static)
CS >
V
HC
, Outputs Open, V
DD
= Max., f = 0
(4)
S202020 202020mA
L101010101010mA
3622 tbl 08

IDT71V424L15PH

Mfr. #:
Manufacturer:
Description:
IC SRAM 4M PARALLEL 44TSOP II
Lifecycle:
New from this manufacturer.
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