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IDT71V424L15PH

P1-P3P4-P6P7-P9
6.42
7
IDT71V424S, IDT71V424L, 3.3V CMOS Static RAM
4 Meg (512K x 8-bit) Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)
(1, 2, 4)
Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)
(1, 4)
NOTES:
1. A write occurs during the overlap of a LOW CS and a LOW WE.
2. OE is continuously HIGH. During a WE controlled write cycle with OE LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and
data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse
is the specified tWP.
3. During this period, I/O pins are in the output state, and input signals must not be applied.
4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high impedance state. CS must be active during the tCW
write period.
5. Transition is measured ±200mV from steady state.
ADDRESS
CS
WE
DATA
OUT
DATA
IN
3622 drw 08
(5)
(2)
(5)
(5)
DATA
IN
VALID
HIGH IMPEDANCE
t
WC
t
AW
t
AS
t
WHZ
t
WP
t
CHZ
t
OW
t
DW
t
DH
t
WR
(3)(3)
CS
ADDRESS
DATA
IN
3622 drw 09
t
AW
t
WC
t
CW
t
AS
t
WR
t
DW
t
DH
DATA
IN
VALID
WE
6.428
IDT71V424S, IDT71V424L, 3.3V CMOS Static RAM
4 Meg (512K x 8-bit) Commercial and Industrial Temperature Ranges
Ordering Information
X
Power
XX
Speed
XXX
Package
X
Process/
Temperature
Range
Blank
I
Commercial (0°C to +70°C)
Industrial (–40°C to +85°C)
Y
PH
36-pin 400 mil SOJ (SO36-1)
44-pin TSOP Type II (SO44-2)
10
12
15
71V424
Device
Type
Speed in nanoseconds
3622 drw 10
S
L
Standard Power
Low Power
X
G
Green
Blank
8
Tube or Tray
Tape and Reel
X
6.42
9
IDT71V424S, IDT71V424L, 3.3V CMOS Static RAM
4 Meg (512K x 8-bit) Commercial and Industrial Temperature Ranges
Datasheet Document History
8/13/99 Updated to new format
Pg. 2 Removed SO44-1 from TSOP pinout
Pg. 7 Revised footnotes on Write Cycle No. 1 diagram
Removed footnote for tWR on Write Cycle No. 2 diagram
Pg. 9 Added Datasheet Document History
8/31/99 Pg. 1–9 Added Industrial temperature range offerings
11/22/02 Pg. 8 Added die revision option to ordering information
07/31/03 Pg. 8 Updated note, L10 speed grade commercial temperature only and updated die stepping from YF to Y.
07/28/04 Pg. 3 Increased ISB for all "L" and S15 speeds by 10mA and increased for S12 speed by 5mA (refer to
PCN# SR-0402-02).
Pg. 8 Added "Restricted hazardous substance device" to the ordering information.
09/20/08 Pg. 1, 8 Added Y and V step part numbers to front page and ordering information. Updated the ordering
information by removing the “IDT” notation.
05/12/09 Pg. 3,5,8 Add Industrial grade for 10ns Low Power.
06/11/09 Pg.1,8 Removed VS, VL from datasheet and ordering information.
09/26/13: Pg.1-9 Removed the /YS & /YL from the device name for the entire datasheet.
Pg.1 Removed IDT's reference to fabrication.
Pg.8 Updated ordering information by adding T&R, updated Restricted Hazardous Substance Device
wording to Green and removed the Die Stepping Revision, the”Y” designator.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
CORPORATE HEADQUARTERS for SALES:
6024 Silver Creek Valley Road 800-345-7015 or
San Jose, CA 95138 408-284-8200
fax: 408-284-2775
www.idt.com
for Tech Support:
sramhelp@idt.com
408-284-4532
P1-P3P4-P6P7-P9

IDT71V424L15PH

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IC SRAM 4M PARALLEL 44TSOP II
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