AD5062
Rev. A | Page 14 of 20
THEORY OF OPERATION
The AD5062 is a single 16-bit, serial input, voltage output DAC.
It operates from supply voltages of 2.7 V to 5.5 V. Data is
written to the AD5062 in a 24-bit word format, via a 3-wire
serial interface.
The AD5062 incorporates a power-on reset circuit that ensures
the DAC output powers up to zero-scale or midscale. The
device also has a software power-down mode pin that reduces
the typical current consumption to less than 1 μA.
DAC ARCHITECTURE
The DAC architecture of the AD5062 consists of two matched
DAC sections. A simplified circuit diagram is shown in
Figure 33. The four MSBs of the 16-bit data-word are decoded
to drive 15 switches, E1 to E15. Each of these switches connects
one of 15 matched resistors to either DACGND or V
REF
buffer
output.
The remaining 12 bits of the data-word drive switches
S0 to S11 of a 12-bit voltage mode R-2R ladder network.
2R
047766-027
S0
V
REF
2R
S1
2R
S11
2R
E1
2R
E2
2R
E15
2R
V
OUT
12-BIT R-2R LADDER FOUR MSBs DECODED INTO
15 EQUAL SEGMENTS
Figure 33. DAC Ladder Structure
REFERENCE BUFFER
The AD5062 operates with an external reference. The reference
input (V
REF
) has an input range of 2 V to V
DD
− 50 mV. This
input voltage is then used to provide a buffered reference for the
DAC core.
SERIAL INTERFACE
The AD5062 has a 3-wire serial interface (
SYNC
, SCLK, and
DIN), which is compatible with SPI, QSPI, and MICROWIRE
interface standards, as well as most DSPs. See for a
timing diagram of a typical write sequence.
Figure 2
The write sequence begins by bringing the
SYNC
line low. Data
from the DIN line is clocked into the 24-bit shift register on the
falling edge of SCLK. The serial clock frequency can be as high
as 30 MHz, making these parts compatible with high speed
DSPs. On the 24th falling clock edge, the last data bit is clocked
in and the programmed function is executed (that is, a change
in the DAC register contents and/or a change in the mode of
operation).
At this stage, the
SYNC
line may be kept low or be brought
high. In either case, it must be brought high for a minimum of
33 ns before the next write sequence so that a falling edge of
SYNC
can initiate the next write sequence. Because the
SYNC
buffer draws more current when V
IN
= 1.8 V than it does when
V
IN
= 0.8 V,
SYNC
should be idled low between write sequences
for even lower power operation of the part. As previously indi-
cated, however, it must be brought high again just before the
next write sequence.
INPUT SHIFT REGISTER
The input shift register is 24 bits wide; see Figure 34. PD1 and
PD0 are control bits that control which mode of operation the
part is in (normal mode or any one of three power-down
modes). There is a more complete description of the various
modes in the Power-Down Modes section. The next 16 bits are
the data bits. These are transferred to the DAC register on the
24th falling edge of SCLK.
SYNC INTERRUPT
In a normal write sequence, the
SYNC
line is kept low for at
least 24 falling edges of SCLK and the DAC is updated on the
24th falling edge. However, if
SYNC
is brought high before the
24th falling edge, this acts as an interrupt to the write sequence.
The shift register is reset and the write sequence is seen as
invalid. Neither an update of the DAC register contents nor a
change in the operating mode occurs; see . Figure 37
DATA BITS
DB15 (MSB) DB0 (LSB)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
NORMAL OPERATION
1kΩ TO GND
100kΩ TO GND
3-STATE
POWER-DOWN MODES
0
0
1
1
0
1
0
1
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0 0 0 0 0 0 PD1 PD0
Figure 34. Input Register Contents
