EVAL-AD5062EBZ Datasheet AD5062BRJZ-1500RL7, EVAL-AD5062EBZ, AD5062BRJZ-1REEL7 | P16-P18

AD5062

Rev. A | Page 15 of 20

POWER-ON TO MIDSCALE OR ZERO SCALE

The AD5062 contains a power-on reset circuit that controls the

output voltage during power-up. The DAC register is filled with

the midscale code and the output voltage is midscale or the

DAC register is filled with the zero-scale code and the output

voltage is zero-scale. It remains there until a valid write

sequence is made to the DAC. This is useful in applications

where it is important to know the state of the output of the DAC

while it is in the process of powering up.

SOFTWARE RESET

The device can be put into software reset by setting all bits in

the DAC register to 1; this includes writing 1s to Bit D23 to

Bit D16, which is not the normal mode of operation. Note that

the

SYNC

interrupt command cannot be performed if a soft-

ware reset command is started.

POWER-DOWN MODES

The AD5062 contains four separate modes of operation. These

modes are software-programmable by setting two bits (DB17

and DB16) in the control register. Table 6 shows how the state

of the bits corresponds to the mode of operation of the device.

Table 6. Modes of Operation for the AD5062

DB17 DB16 Operating Mode

0 0 Normal operation

Power-down mode:

0 1 3-state

1 0 100 kΩ to GND

1 1 1 kΩ to GND

When both bits are set to 0, the part works normally with its

normal power consumption. However, for the three power-

down modes, the supply current falls to less than 1 A at 5.5 V.

Not only does the supply current fall, but the output stage is

also internally switched from the output of the DAC to a

resistor network of known values. This has the advantage that

the output impedance of the part is known while the part is in

power-down mode. There are three different options. The

output is connected internally to GND through a 1 kΩ resistor

or a 100 kΩ resistor, or it is left open-circuited (3-state). The

output stage is illustrated in Figure 35.

POWER-DOWN

CIRCUITRY

AD5062

DAC

04766-029

OUT

RESISTOR

NETWORK

Figure 35. Output Stage During Power-Down

The bias generator, the DAC core, and other associated linear

circuitry are all shut down when the power-down mode is

activated. However, the contents of the DAC register are unaf-

fected when in power-down. The time to exit power-down is

typically 2.5 µs for V

= 5 V, and 5 µs for V

= 3 V; see Figure 19.

MICROPROCESSOR INTERFACING

AD5062 to ADSP-2101/ADSP-2103 Interface

Figure 36 shows a serial interface between the AD5062 and the

ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103 should

be set up to operate in the SPORT transmit alternate framing

mode. The ADSP-2101/ADSP-2103 SPORT is programmed

through the SPORT control register and should be configured

as follows: internal clock operation, active low framing, 16-bit

word length. Transmission is initiated by writing a word to the

Tx register after the SPORT has been enabled.

AD5062

ADDITIONAL PINS OMITTED FOR CLARITY

TFS

SCLK

SYNC

DIN

SCLK

04766-030

ADSP-2101/

ADSP-2103

Figure 36. AD5062 to ADSP-2101/ADSP-2103 Interface

04766-031

DB23 DB23 DB0DB0

INVALID WRITE SEQUENCE:

SYNC HIGH BEFORE 24

FALLING EDGE

VALID WRITE SEQUENCE, OUTPUT UPDATES

ON THE 24

FALLING EDGE

SYNC

SCLK

DIN

Figure 37.

SYNC

Interrupt Facility

AD5062

Rev. A | Page 16 of 20

AD5062 to 68HC11/68L11 Interface

Figure 38 shows a serial interface between the AD5062 and the

68HC11/68L11 microcontroller. SCK of the 68HC11/68L11

drives the SCLK pin of the AD5062, while the MOSI output

drives the serial data line of the DAC. The

SYNC

signal is

derived from a port line (PC7). The setup conditions for correct

operation of this interface require that the 68HC11/68L11 be

configured so that its CPOL bit is 0 and its CPHA bit is 1. When

data is being transmitted to the DAC, the

SYNC

line is taken

low (PC7). When the 68HC11/68L11 is configured where its

CPOL bit is 0 and its CPHA bit is 1, data appearing on the

MOSI output is valid on the falling edge of SCK. Serial data

from the 68HC11/68L11 is transmitted in 8-bit bytes with only

eight falling clock edges occurring in the transmit cycle. Data is

transmitted MSB first. In order to load data to the AD5062,

PC7 is left low after the first eight bits are transferred, and a

second serial write operation is performed to the DAC, and PC7

is taken high at the end of this procedure.

AD5062

ADDITIONAL PINS OMITTED FOR CLARITY

PC7

SCK

MOSI

SYNC

SCLK

DIN

04766-032

68HC11/

68L11

Figure 38. AD5062 to 68HC11/68L11 Interface

AD5062 to Blackfin® ADSP-BF53x Interface

Figure 39 shows a serial interface between the AD5062 and the

Blackfin ADSP-53x microprocessor. The ADSP-BF53x proces-

sor family incorporates two dual-channel synchronous serial

ports, SPORT1 and SPORT0, for serial and multiprocessor

communications. Using SPORT0 to connect to the AD5062,

the setup for the interface is: DT0PRI drives the SDIN pin of

the AD5062, while TSCLK0 drives the SCLK of the part; the

SYNC

is driven from TFS0.

ADSP-BF53x

AD5062

ADDITIONAL PINS OMITTED FOR CLARITY

DT0PRI

TSCLK0

TFS0

DIN

SCLK

SYNC

04766-033

Figure 39. AD5062 to Blackfin ADSP-BF53x Interface

AD5062 to 80C51/80L51 Interface

Figure 40 shows a serial interface between the AD5062 and the

80C51/80L51 microcontroller. The setup for the interface is:

TxD of the 80C51/80L51 drives SCLK of the AD5062 while

RxD drives the serial data line of the part. The

SYNC

signal is

again derived from a bit-programmable pin on the port. In this

case, Port Line P3.3 is used. When data is to be transmitted to

the AD5062, P3.3 is taken low. The 80C51/80L51 transmits data

only in 8-bit bytes; thus only eight falling clock edges occur in

the transmit cycle. To load data to the DAC, P3.3 is left low after

the first eight bits are transmitted, and a second write cycle is

initiated to transmit the second byte of data. P3.3 is taken high

following the completion of this cycle. The 80C51/80L51

outputs the serial data in a format that has the LSB first. The

AD5062 requires its data with the MSB as the first bit received;

the 80C51/80L51 transmit routine should take this into account.

80C51/80L51

AD5062

ADDITIONAL PINS OMITTED FOR CLARITY

P3.3

TxD

RxD

SYNC

SCLK

DIN

04766-034

Figure 40. AD5062 to 80C51/80L51 Interface

AD5062 to MICROWIRE Interface

Figure 41 shows an interface between the AD5062 and any

MICROWIRE-compatible device. Serial data is shifted out on

the falling edge of the serial clock and is clocked into the

AD5062 on the rising edge of the SK.

MICROWIRE

AD5062

ADDITIONAL PINS OMITTED FOR CLARITY

SYNC

SCLK

DIN

04766-035

Figure 41. AD5062 to MICROWIRE Interface

AD5062

Rev. A | Page 17 of 20

APPLICATIONS

CHOOSING A REFERENCE FOR THE AD5062

To achieve the optimum performance from the AD5062,

thought should be given to the choice of a precision voltage

reference. The AD5062 has just one reference input, V

REF

. The

voltage on the reference input is used to supply the positive

input to the DAC. Therefore, any error in the reference is

reflected in the DAC.

There are four possible sources of error when choosing a

voltage reference for high accuracy applications: initial

accuracy, ppm drift, long-term drift, and output voltage noise.

Initial accuracy on the output voltage of the DAC will lead to a

full-scale error in the DAC. To minimize these errors, a refer-

ence with high initial accuracy is preferred. Also, choosing a

reference with an output trim adjustment, such as the ADR43x

family, allows a system designer to trim out system errors by

setting a reference voltage to a voltage other than the nominal.

The trim adjustment can also be used at the operating

temperature to trim out any error.

Because the supply current required by the AD5062 is

extremely low, the parts are ideal for low supply applications.

The ADR395 voltage reference is recommended. This requires

less than 100 μA of quiescent current and can, therefore, drive

multiple DACs in one system, if required. It also provides very

good noise performance at 8 μV p-p in the 0.1 Hz to 10 Hz range.

04766-036

AD5062

SYNC

SCLK

DIN

OUT

= 0V TO 5V

ADR395

3-WIRE

SERIAL

INTERFACE

Figure 42. ADR395 as Reference to AD5062

Long-term drift is a measure of how much the reference drifts

over time. A reference with a tight long-term drift specification

ensures that the overall solution remains relatively stable during

its entire lifetime. The temperature coefficient of a reference’s

output voltage affects INL, DNL, and TUE. A reference with a

tight temperature coefficient specification should be chosen to

reduce temperature dependence of the DAC output voltage on

ambient conditions.

In high accuracy applications, which have a relatively low noise

budget, reference output voltage noise needs to be considered. It

is important to choose a reference with as low an output noise

voltage as practical for the system noise resolution required.

Precision voltage references, such as the ADR435, produce low

output noise in the 0.1 Hz to 10 Hz region. Table 7 shows

examples of recommended precision references for use as

supply to the AD5062.

Table 7. Precision References Part List for the AD5062

Part

No.

Initial

Accuracy

(mV max)

Temperature

Drift

(ppm/°C max)

0.1 Hz to 10 Hz

Noise (μV p-p typ)

ADR435 ±2 3 (SO-8) 8

ADR425 ±2 3 (SO-8) 3.4

ADR02 ±3 3 (SO-8)

ADR02 ±3 3 (SC70)

ADR395 ±5 9 (TSOT-23) 8

BIPOLAR OPERATION USING THE AD5062

The AD5062 has been designed for single-supply operation, but

a bipolar output range is also possible using the circuit in

Figure 43. The circuit shown yields an output voltage range of

±5 V. Rail-to-rail operation at the amplifier output is achievable

using an AD820/AD8032 or an OP196/OP295.

The output voltage for any input code can be calculated as

follows:

⎥

⎦

⎤

⎢

⎣

⎡

⎟

⎠

⎞

⎜

⎝

⎛

×−

⎟

⎠

⎞

⎜

⎝

⎛

⎟

⎠

⎞

⎜

⎝

⎛

×=

2R1RD

DDDD

65536

where D represents the input code in decimal (0–65536).

With V

REF

= 5 V, R1 = R2 = 10 kΩ:

65536

−

⎟

⎠

⎞

⎜

⎝

⎛

This is an output voltage range of ±5 V with 0x0000

corresponding to a −5 V output and 0xFFFF corresponding to a

+5 V output.

AD5062

+5V

10µF

04766-037

R1 = 10kΩ

OUT

REF

0.1µF

3-WIRE

SERIAL

INTERFACE

AD820/

OP295

–

–5V

+5V

R2 = 10k

Ω

±5V

Figure 43. Bipolar Operation with the AD5062

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21

EVAL-AD5062EBZ

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