AD5062
Rev. A | Page 3 of 20
SPECIFICATIONS
V
DD
= 5.5 V, V
REF
= 4.096 V, R
L
= Unloaded, C
L
= 22 pF to GND; T
MIN
to T
MAX
, unless otherwise noted.
Table 2.
A,B Grade
1
Parameter Min Typ Max Unit Test Conditions/Comments
STATIC PERFORMANCE
Resolution 16 Bits
Relative Accuracy (INL)
2
±0.5 ±1 LSB −40°C to +85°C, B grade
±0.5 ±2 −40°C to +85°C, A grade
Total Unadjusted Error (TUE) ±500 ±800 μV −40°C to +85°C, B grade
±500 ±800 −40°C to +85°C, A grade
Differential Nonlinearity (DNL) ±0.5 ±1 LSB Guaranteed monotonic
−40°C to +85°C, B grade
±0.5 ±1 Guaranteed monotonic
−40°C to +85°C, A grade
Gain Error ±0.01 ±0.02 % of FSR T
A
= −40°C to +85°C B grade
±0.01 ±0.02 T
A
= −40°C to +85°C A grade
Gain Error Temperature Coefficient 1 ppm of FSR/°C
Offset Error ±0.025 ±0. 05 mV T
A
= −40°C to + 85°C, B grade
±0.025 ±0. 05 T
A
= −40°C to + 85°C, A grade
Offset Error Temperature Coefficient 0.5 μV/°C
Full-Scale Error ±500 ±800 μV
All 1s loaded to DAC register, B grade
T
A
= −40°C to +85°C
±500 ±800
All 1s loaded to DAC register, A grade
T
A
= −40°C to +85°C
OUTPUT CHARACTERISTICS
3
Output Voltage Range 0 V
REF
V Unipolar operation
Output Voltage Settling Time 4 μs
¼ scale to ¾ scale code transition to
±1LSB.
Output Noise Spectral Density 24
nV/Hz
DAC code = midscale, 1 kHz
Output Voltage Noise 6 μV p-p
DAC code = midscale, 0.1 to 10 Hz
bandwidth
Digital-to-Analog Glitch Impulse 2 nV-s 1 LSB change around major carry
Digital Feedthrough 0.1 nV-s
DC Output Impedance (Normal) 8
Output impedance tolerance ±20%
DC Output Impedance (Power-Down)
(Output Connected to 1 kΩ Network) 1 Output impedance tolerance ±20%
(Output Connected to 100 kΩ Network) 100 Output impedance tolerance ±20%
REFERENCE INPUT/ OUTPUT
V
REF
Input Range
2
2 V
DD
− 50 mV
Input Current (Power-Down) ±0.1 μA Zero-scale loaded
Input Current (Normal) ±0. 5 μA
DC Input Impedance 1
MΩ
Bipolar/unipolar operation
LOGIC INPUTS
Input Current
4
±1 ±2 μA
V
IL
, Input Low Voltage 0.8 V V
DD
= 4.5 V to 5.5 V
0.8 V
DD
= 2.7 V to 3.6 V
V
IH
, Input High Voltage 2.0 V V
DD
= 2.7 V to 5.5 V
1.8 V
DD
= 2.7 V to 3.6 V
Pin Capacitance 4 pF
AD5062
Rev. A | Page 4 of 20
A,B Grade
1
Parameter Min Typ Max Unit Test Conditions/Comments
POWER REQUIREMENTS
V
DD
2.7 5.5 V All digital inputs at 0 V or V
DD
I
DD
(Normal Mode) DAC active and excluding load current
V
DD
= 2.7 V to 5.5 V 0.65 0.7 mA
V
IN
= V
DD
and V
IL
= GND, V
DD
= 5.5 V,
V
REF
= 4.096 V, code = midscale
I
DD
(All Power-Down Modes)
V
DD
= 2.5 V to 5.5 V 1 μA
V
IH
= V
DD
and V
IL
= GND V
DD
= 5.5 V,
V
REF
= 4.096 V, code = midscale
Power Supply Rejection Ratio (PSRR) 0.5 LSB ∆V
DD
± 10%, V
DD
= 5 V, unloaded
1
Temperature range for the B grade: −40°C to +85°C, typical at 25°C; temperature range for the Y grade: −40°C to +125°C.
2
Refer to Figure 27, Figure 28, Figure 29, Figure 30, and Figure 31 for device performance under lower supply and reference voltage conditions.
3
Guaranteed by design and characterization, not production tested.
4
Total current flowing into all pins.
AD5062
Rev. A | Page 5 of 20
TIMING CHARACTERISTICS
V
DD
= 2.7 V to 5.5 V; all specifications T
MIN
to T
MAX
,
unless otherwise noted.
Table 3.
Parameter Limit
1
Unit Test Conditions/Comments
t
1
2
33 ns min SCLK cycle time
t
2
5 ns min SCLK high time
t
3
3 ns min SCLK low time
t
4
10 ns min
SYNC to SCLK falling edge setup time
t
5
3 ns min Data setup time
t
6
2 ns min Data hold time
t
7
0 ns min
SCLK falling edge to SYNC rising edge
t
8
12 ns min
Minimum SYNC high time
t
9
9 ns min
SYNC rising edge to next SCLK fall ignore
1
All input signals are specified with tr = tf = 1 ns/V (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
2
Maximum SCLK frequency is 30 MHz.
t
4
t
3
t
2
t
5
t
7
t
6
D0D1D2D22D23
SYNC
SCLK
04766-002
t
9
t
1
t
8
D23 D22DIN
Figure 2. Timing Diagram

EVAL-AD5062EBZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Data Conversion IC Development Tools EVAL BRD - AD5062
Lifecycle:
New from this manufacturer.
Delivery:
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