16
M68000 USER’S MANUAL ADDENDUM
MOTOROLA
8.0 MC68SEC000 AC ELECTRICAL SPECIFICATIONS — BUS
ARBITRATION
Add the following table and Figure 11 to Section 10.17.
(GND = 0 Vdc; T
A
= T
L
to T
H
; refer to Figure 13)
Applies to 3.3V and 5V.
1. The minimum value must be met to guarantee proper operation. If the maximum value is exceeded, BG
may be reasserted.
NUM CHARACTERISTICp
10MHz 16MHz 20MHz
UNIT
MIN MAX MIN MAX MIN MAX
7 Clock High to Address, Data Bus High Impedance (Maximum) 55 50 42 ns
16 Clock High to Control Bus High Impedance 55 50 42 ns
33 Clock High to BG
Asserted 0 35 0 30 0 25 ns
34 Clock High to BG
Negated 0 35 0 30 0 25 ns
35 BR
Asserted to BG Asserted 1.5 3.5 1.5 3.5 1.5 3.5 Clks
36 BR
Negated to BG Negated 1.5 3.5 1.5 3.5 1.5 3.5 Clks
38 BG
Asserted to Control, Address, Data Bus High Impedance (AS
Negated)
—55—50—42ns
39 BG
Width Negated 1.5 1.5 1.5 Clks
47 Asynchronous Input Setup Time 5—5—5—ns
58
1
BR
Negated to AS, LDS, UDS, R/W Driven 1.5 1.5 1.5 Clks
58A
1
BR
Negated to FC Driven 1—1—1—Clks
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MOTOROLA
M68000 USER’S MANUAL ADDENDUM
17
Figure 11. Bus Arbitration Timing
Figure 12. MC68SEC000 Bus Arbitration Timing Diagram
36
3934
38
33
35
CLK
NOTE: Setup time to the clock (#47) for the asynchronous inputs BERR, BR, DTACK, IPL2-IPL0, and VPA
guarantees their recognition at the next falling edge of the clock.
BR
BG
AND R/W
STROBES
CLK
33
35
BR
BG
AS
DS
R/W
FC2–FC0
A19–A0
D7–D0
47
38
36
58
NOTE: Waveform measurements for all inputs and outputs are specified at: logic high 2.0 V, logic low = 0.8 V.
34
58A
39
A23
D15
LDS/UDS
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18
M68000 USER’S MANUAL ADDENDUM
MOTOROLA
Figure 13. Bus Arbitration Timing—Idle Bus Case
CLK
47
35
34
38
BR
BG
AS
DS
VMA
R/W
FC2-FC0
A23-A0
D15-D0
NOTES: Waveform measurements for all inputs and outputs are specified at: logic high 2.0 V, logic low = 0.8 V. This diagram also applies to the 68EC000.
33
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cale Semiconductor,
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MC68EC000CAA20

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
IC MPU M680X0 20MHZ 64QFP
Lifecycle:
New from this manufacturer.
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