MC68EC000CAA20 Datasheet MC68EC000EI12R2, MC68EC000CAA16, MC68EC000EI16 | P4-P6

M68000 USER’S MANUAL ADDENDUM

MOTOROLA

2.0 SIGNAL DESCRIPTION

Change Figure 3-3 on Page 3-2.

Figure 1. Input and Output Signals (MC68EC000 and MC68SEC000)

2.1 Data Bus (D15-D0)

In Section 3.2 on page 3-4, replace “The MC68EC000 and MC68HC001 use D7-D0 in 8-bit mode, and D15-

D8 are undefined.” with “Using the MC68HC001, MC68EC000, and MC68SEC000 mode pin, you can

statically select either 8- or 16-bit modes for data transfer. The MC68EC000, MC68SEC000, and

MC68HC001 use D7-D0 in 8-bit mode. D15-D8 are undefined.”

2.2 Bus Arbitration Control

In Section 3.4 on page 3-5, the sentence “In the 48-pin version of the MC68008 and MC68EC000, no pin is

available for the bus grant acknowledge signal; this microprocessor uses a two-wire bus arbitration

scheme.” should read “In the 64-pin MC68EC000 and MC68SEC000, no pin is available for the bus grant

acknowledge signal. These microprocessors use a two-wire bus arbitration scheme.”

2.3 System Control

The Mode subsection heading of Section 3.6 on page 3-7 should read ‘‘Mode (MODE) (MC68HC001/

68EC000/68SEC000).’’

2.4 MC68SEC000 Low-Power Mode

Add the following to Sections 4 and 5, Bus Operation.

The MC68SEC000 has been redesigned to provide fully static- and low-power operation. This section

describes the recommended method for placing the MC68SEC000 into a low-power mode to reduce the

ADDRESS BUS

DATA BUS

ASYNCHRONOUS

BUS CONTROL

BUS ARBITRATION

CONTROL

INTERRUPT

CONTROL

PROCESSOR

STATUS

A23-A0

D15-D0

R/W

UDS

LDS

DTACK

BERR

RESET

HALT

MODE

SYSTEM

CONTROL

GND

CLK

MC68SEC000

FC0

FC1

FC2

IPL0

IPL1

IPL2

AVEC

Frees

cale Semiconductor,

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

nc...

M68000 USER’S MANUAL ADDENDUM

MOTOROLA

power consumption to its quiescent value

while maintaining the internal state of the processor. The

low-power mode described below will be routinely tested as part of the MC68SEC000 test vectors provided

by Motorola.

To successfully enter the low-power mode, the MC68SEC000 must first be in the supervisor mode. A

recommended method for entering the low-power mode is to use the TRAP instruction, which causes the

processor to begin exception processing, thus entering the supervisor mode. External circuitry should

accomplish the following steps during the trap routine:

1. Externally detect a write to the low-power address. You select this address which can be any address

in the 16 Mbyte addressing range of the MC68SEC000. A write to the low-power address can be

detected by polling A23–A0, R/W

, and FC2–FC0. When the low-power address is detected, R/W is

a logic low, and the function codes have a five (101) on their output, the processor is writing to the

low-power address in supervisor mode and user-designed circuitry should assert the

ADDRESS_MATCH signal shown in Figure 2 and Figure 3.

Figure 3. MC68SEC000 Low-Power Circuitry for 8-Bit Data Bus

2. Execute the STOP instruction. The external circuitry shown in Figure 2 and Figure 3 will count the

number of bus cycles starting with the write to the low-power address and will stop the processor

clock on the first falling edge of the system clock after the bus cycle that reads the immediate data

of the STOP instruction. Figure 3 has one more flip-flop than Figure 2 because the MC68SEC000 in

The preliminary speciﬁcation for the MC68SEC000’s current drain while in the low-power mode is Idd < 2

A for 3.3V operation and

Idd < 5

A for 5.0V operation.

Figure 2. MC68SEC000 Low-Power Circuitry for 16-Bit Data Bus

ADDRESS_MATCH

RESTART

RESET

CPU_CLK

SYSTEM_CLK

ADDRESS_MATCH

RESTART

RESET

CPU_CL

SYSTEM_CLK

AS AS AS

Frees

cale Semiconductor,

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

nc...

M68000 USER’S MANUAL ADDENDUM

MOTOROLA

8-bit mode requires two bus cycles to fetch the immediate data of the STOP instruction. After the

processor clock is disabled, it is often necessary to disable the clock to other sections of your circuit.

This can be done, but be careful that runt clocks and spurious glitches are not presented to the

MC68SEC000. A timing diagram is shown in Figure 4.

Figure 4. MC68SEC000 Clock Stop Timing for 16-Bit Data Bus

Note:

While the MC68SEC000 is in the low-power mode, all inputs must be driven to V

or V

, or have a

pull-up or pull-down resistor.

3. This step is optional depending on whether your applications require the MC68SEC000 signals with

three-state capability to be placed into a high-impedance state. To place the MC68SEC000 into a

three-state condition, the proper method for arbitrating the bus (as described in

5.2 Bus Arbitration

in the

M68000 User’s Manual, Rev 8

)

hould be completed during the fetch of the status register data

for the STOP instruction. A timing diagram with the bus arbitration sequence is shown in Figure 5.

Figure 5. MC68SEC000 Clock Stop Timing with Bus Arbitration for 16-Bit Data Bus

Write to

Low-Power

Address

Fetch Immediate

Data of STOP

Instruction

Stop

CLK

S0 S1 S2 S3 S4 S5 S6 S7S0 S1 S2 S3 S4 S5 S6 S7

CPU_CLK

DTACK

CLK

S0 S1 S2 S3 S4 S5 S6 S7S0 S1 S2 S3 S4 S5 S6 S7

CPU_CLK

DTACK

Write to

Low-Power

ess

Fetch Immediate

Data of STOP

Instruction

Stop

Frees

cale Semiconductor,

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

nc...

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P26

MC68EC000CAA20

Mfr. #:

Buy MC68EC000CAA20

Manufacturer:

NXP Semiconductors

Description:

IC MPU M680X0 20MHZ 64QFP

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

MC68EC000CAA20

MC68EC000CAA20

Products related to this Datasheet