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EP9301-CQZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42
4 Copyright 2010 Cirrus Logic (All Rights Reserved) DS636F2
EP9301
Entry Level ARM9 System-on-Chip Processor
List of Figures
Figure 1. Timing Diagram Drawing Key .................................................................................13
Figure 2. SDRAM Load Mode Register Cycle Timing Measurement .....................................14
Figure 3. SDRAM Burst Read Cycle Timing Measurement ...................................................15
Figure 4. SDRAM Burst Write Cycle Timing Measurement ...................................................16
Figure 5. SDRAM Auto Refresh Cycle Timing Measurement ................................................17
Figure 6. Static Memory Multiple Word Read 8-bit Cycle Timing Measurement ....................18
Figure 7. Static Memory Multiple Word Write 8-bit Cycle Timing Measurement ....................19
Figure 8. Static Memory Multiple Word Read 16-bit Cycle Timing Measurement ..................20
Figure 9. Static Memory Multiple Word Write 16-bit Cycle Timing Measurement ..................21
Figure 10. Static Memory Burst Read Cycle Timing Measurement .......................................22
Figure 11. Static Memory Burst Write Cycle Timing Measurement .......................................23
Figure 12. Static Memory Single Read Wait Cycle Timing Measurement .............................24
Figure 13. Static Memory Single Write Wait Cycle Timing Measurement ..............................25
Figure 14. Static Memory Turnaround Cycle Timing Measurement .......................................26
Figure 15. Ethernet MAC Timing Measurement .....................................................................28
Figure 16. TI Single Transfer Timing Measurement ...............................................................29
Figure 17. Microwire Frame Format, Single Transfer ............................................................29
Figure 18. SPI Format with SPH=1 Timing Measurement .....................................................30
Figure 19. Inter-IC Sound (I2S) Timing Measurement ...........................................................31
Figure 20. AC ‘97 Configuration Timing Measurement ..........................................................32
Figure 21. ADC Transfer Function .........................................................................................33
Figure 22. JTAG Timing Measurement ..................................................................................34
DS636F2 Copyright 2010 Cirrus Logic (All Rights Reserved) 5
EP9301
Entry Level ARM9 System-on-Chip Processor
List of Tables
Table A. Change History .......................................................................................................... 2
Table B. General Purpose Memory Interface Pin Assignments .............................................. 6
Table C. Ethernet Media Access Controller Pin Assignments ................................................. 7
Table D. Audio Interfaces Pin Assignment .............................................................................. 7
Table E. 12-bit Analog-to-Digital Converter Pin Assignments ................................................. 7
Table F. Universal Asynchronous Receiver/Transmitters Pin Assignments ............................ 8
Table G.Dual Port USB Host Pin Assignments ....................................................................... 8
Table H. Two-Wire Port with EEPROM Support Pin Assignments .......................................... 8
Table I. Real-Time Clock with Pin Assignments ..................................................................... 8
Table J. PLL and Clocking Pin Assignments .......................................................................... 9
Table K. Interrupt Controller Pin Assignment .......................................................................... 9
Table L. Dual LED Pin Assignments ....................................................................................... 9
Table M.General Purpose Input/Output Pin Assignment ........................................................ 9
Table N. Reset and Power Management Pin Assignments ................................................... 10
Table O.Hardware Debug Interface ...................................................................................... 10
Table P. Pin List in Numerical Order by Pin Number ............................................................. 36
Table Q.Pin Description ...................................................................................................... 38
Table R. Pin Multiplex Usage Information ............................................................................. 39
6 Copyright 2010 Cirrus Logic (All Rights Reserved) DS636F2
EP9301
Entry Level ARM9 System-on-Chip Processor
Processor Core - ARM920T
The ARM920T is a Harvard architecture processor with
separate 16-kbyte instruction and data caches with an 8-
word line length but a unified memory. The processor
utilizes a five-stage pipeline consisting of fetch, decode,
execute, memory, and write stages. Key features include:
• ARM (32-bit) and Thumb (16-bit compressed)
instruction sets
• 32-bit Advanced Micro-Controller Bus Architecture
(AMBA)
• 16 kbyte Instruction Cache with lockdown
• 16 kbyte Data Cache (programmable write-through or
write-back) with lockdown
• MMU for Linux
®
, Microsoft
®
Windows
®
CE and other
operating systems
• Translation Look Aside Buffers with 64 Data and 64
Instruction Entries
• Programmable Page Sizes of 1 Mbyte, 64 kbyte,
4 kbyte, and 1 kbyte
• Independent lockdown of TLB Entries
MaverickKey
™
Unique ID
MaverickKey unique hardware programmed IDs are a
solution to the growing concern over secure web content
and commerce. With Internet security playing an
important role in the delivery of digital media such as
books or music, traditional software methods are quickly
becoming unreliable. The MaverickKey unique IDs
provide OEMs with a method of utilizing specific
hardware IDs such as those assigned for SDMI (Secure
Digital Music Initiative) or any other authentication
mechanism.
Both a specific 32-bit ID as well as a 128-bit random ID is
programmed into the EP9301 through the use of laser
probing technology. These IDs can then be used to
match secure copyrighted content with the ID of the
target device the EP9301 is powering, and then deliver
the copyrighted information over a secure connection. In
addition, secure transactions can benefit by also
matching device IDs to server IDs. MaverickKey IDs
provide a level of hardware security required for today’s
Internet appliances.
General Purpose Memory Interface (SDRAM,
SRAM, ROM, FLASH)
The EP9301 features a unified memory address model
where all memory devices are accessed over a common
address/data bus. Memory accesses are performed via
the Processor bus. The SRAM memory controller
supports 8- and 16-bit devices and accommodates an
internal boot ROM concurrently with 16-bit SDRAM
memory.
• 1 to 4 banks of 16-bit, 66 MHz SDRAM
• Address and data bus shared between SDRAM,
SRAM, ROM, and FLASH memory
• NOR FLASH memory supported
Table B. General Purpose Memory Interface Pin Assignments
Pin Mnemonic Pin Description
SDCLK SDRAM Clock
SDCLKEN SDRAM Clock Enable
SDCSn[3:0] SDRAM Chip Selects 3-0
RASn SDRAM RAS
CASn SDRAM CAS
SDWEn SDRAM Write Enable
CSn[7:6] and CSn[3:0] Chip Selects 7, 6, 3, 2, 1, 0
AD[25:0] Address Bus 25-0
DA[15:0] Data Bus 15-0
DQMn[1:0] SDRAM Output Enables / Data Masks
WRn SRAM Write Strobe
RDn SRAM Read / OE Strobe
WAITn SRAM Wait Input
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42

EP9301-CQZ

Mfr. #:
Buy EP9301-CQZ
Manufacturer:
Cirrus Logic
Description:
Microprocessors - MPU IC Entry-Level ARM9 SOC Processor
Lifecycle:
New from this manufacturer.
Delivery:
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