IS62WV12816DALL/DBLL, IS65WV12816DALL/DBLL
10 Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
05/29/2013
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,2)
(Over Operating Range)
35 ns 45 ns 55 ns
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
tWc Write Cycle Time 35 — 45 — 55 — ns
tScS1/tScS2 CS1/CS2 to Write End 25 — 35 — 45 — ns
tAW Address Setup Time to Write End 25 — 35 — 45 — ns
tHA Address Hold from Write End 0 — 0 — 0 — ns
tSA Address Setup Time 0 — 0 — 0 — ns
tPWB LB, UB Valid to End of Write 30 — 35 — 45 — ns
tPWe WE Pulse Width 30 — 35 — 40 — ns
tSd Data Setup to Write End 15 — 20 — 25 — ns
tHd Data Hold from Write End 0 — 0 — 0 — ns
tHzWe
(3)
WE LOW to High-Z Output — 20 — 20 — 20 ns
tLzWe
(3)
WE HIGH to Low-Z Output 5 — 5 — 5 — ns
Notes:
1. Test conditions and output loading conditions are specified in the AC Test Conditions and AC Test Loads (Figure 1).
2. The internal write time is defined by the overlap of CS1 LOW, CS2 HIGH and UB or LB, and WE LOW. All signals must be in
valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are
referenced to the rising or falling edge of the signal that terminates the write.
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
