Integrated Silicon Solution, Inc. — www.issi.com 13
Rev. C
05/29/2013
IS62WV12816DALL/DBLL, IS65WV12816DALL/DBLL
DATA-IN VALID
DATA UNDEFINED
t
WC
t
SCS1
t
SCS2
t
AW
t
HA
t
PWE
t
HZWE
HIGH-Z
t
LZWE
t
SA
t
SD
t
HD
ADDRESS
OE
CS1
CS2
WE
LB, UB
DOUT
DIN
AC WAVEFORMS
WRITE CYCLE NO. 3 
(WE Controlled: OE is LOW During Write Cycle)
IS62WV12816DALL/DBLL, IS65WV12816DALL/DBLL
14 Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
05/29/2013
DATA UNDEFINED
t
WC
ADDRESS 1 ADDRESS 2
t
WC
HIGH-Z
t
PBW
WORD 1
LOW
WORD 2
t
HD
t
SA
t
HZWE
ADDRESS
CS1
UB, LB
WE
D
OUT
D
IN
OE
DATA
IN
VALID
t
LZWE
t
SD
t
PBW
DATA
IN
VALID
t
SD
t
HD
t
SA
t
HA t
HA
UB_CSWR4.eps
HIGH
CS2
AC WAVEFORMS
WRITE CYCLE NO. 4 
(UB/LB Controlled)
Integrated Silicon Solution, Inc. — www.issi.com 15
Rev. C
05/29/2013
IS62WV12816DALL/DBLL, IS65WV12816DALL/DBLL
DATA RETENTION SWITCHING CHARACTERISTICS
Symbol  Parameter  Test Condition  Min. Max. Unit
Vdr Vdd for Data Retention See Data Retention Waveform 1.5 3.6 V
Idr Data Retention Current Vdd = Vdr(min), Com. 4 µA
(1) 0V < CS2 < 0.2V, or Ind. 6 µA
(2) CS1 Vdd – 0.2V, CS2 > Vdd - 0.2V or Auto. 20 µA
(3) LB and UB > Vdd -0.2V, CS1 < 0.2V, CS2 > Vdd - 0.2V typ.
(2)
2 µA
tSdr Data Retention Setup Time See Data Retention Waveform 0 ns
trdr Recovery Time See Data Retention Waveform trc ns
Note:
1. Typical values are measured at V
dd = Vdr(min), TA = 25
o
C and not 100% tested.
DATA RETENTION WAVEFORM (CS2 Controlled)
CS2 0.2V
tSDR tRDR
V
DR
CS2
GND
Data Retention Mode
VDD

IS62WV12816DBLL-45BLI

Mfr. #:
Manufacturer:
ISSI
Description:
SRAM 2Mb A128K x 1645ns Async SRAM
Lifecycle:
New from this manufacturer.
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