Si5022/Si5023
Rev. 1.23 21
Pin Descriptions: Si5022/23
Figure 17. Si5022/23 Pin Configuration
Table 9. Si5022/23 Pin Descriptions
Pin # Pin Name I/O Signal Level Description
1,2 RATESEL0,
RATESEL1
ILVTTLData Rate Select.
These pins configure the onboard PLL for clock and
data recovery at one of four user selectable data
rates. See Table 7 for configuration settings.
Note: These inputs have weak internal pullups.
3LOS_LVLI LOS Level Control.
The LOS threshold is set by the input voltage level
applied to this pin. Figure 6 on page 15 shows the
input setting to output threshold mapping.
LOS is disabled when the voltage applied is less
than 1 V.
4 SLICE_LVL I Slicing Level Control.
The slicing threshold level is set by applying a volt-
age to this pin as described in the Slicing Level sec-
tion of the data sheet. If this pin is tied to GND,
slicing level adjustment is disabled, and the slicing
level is set to the midpoint of the differential input
signal on DIN. Slicing level becomes active when
the voltage applied to the pin is greater than
500 mV.
5
6
REFCLK+
REFCLK–
ISee Table2Differential Reference Clock (Optional).
When present, the reference clock sets the center
operating frequency of the DSPLL for clock and
data recovery. Tie REFCLK+ to VDD and REFCLK–
to GND to operate without an external reference
clock.
See Table 8 for typical reference clock frequencies.
1
RATESEL0
GND
Pad
Top View
2
3
4
5
6
7
21
20
19
18
17
16
15
141312111098
22232425262728
RATESEL1
LOS_LVL
SLICE_LVL
REFCLK+
REFCLK-
LOL
VDD
REXT
RESET/CAL
VDD
DOUT+
DOUT-
GND
BERMON
BER_ALM
BER_LVL
VDD
CLKDSBL
CLKOUT+
CLKOUT-
LTR
LOS
DSQLCH
VDD
DIN+
DIN-
VDD
