Si5022/Si5023
Rev. 1.23 9
Input Voltage High (LVTTL Inputs) V
IH
2.0 — — V
Input Low Current (LVTTL Inputs) I
IL
——10µA
Input High Current (LVTTL Inputs) I
IH
——10µA
Input Impedance (LVTTL Inputs) R
IN
10 — — kΩ
LOS_LVL, BER_LVL, SLICE_LVL Input
Impedance
R
IN
75 100 125 kΩ
Output Voltage Low (LVTTL Outputs) V
OL
I
O
= 2 mA — — 0.4 V
Output Voltage High (LVTTL Outputs) V
OH
I
O
= 2 mA 2.0 — — V
Table 3. AC Characteristics (Clock and Data)
(V
DD
= 2.5 V ±5% for Si5022 or 3.3 V ±5% for Si5023, T
A
= –40 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Unit
Output Clock Rate f
CLK
.154 — 2.7 GHz
Output Clock Rise Time—OC-48 t
R
Figure 3 on page 6 — 70 90 ps
Output Clock Fall Time—OC-48 t
F
Figure 3 on page 6 — 70 90 ps
Output Clock Duty Cycle
OC-48/12/3
48 50 52 % of
UI
Output Data Rise Time—OC-48 t
R
Figure 3 on page 6 — 80 110 ps
Output Data Fall Time—OC-48 t
F
Figure 3 on page 6 — 80 110 ps
Clock-to-Data Delay
FEC (2.7 GHz)
OC-48
GbE
OC-12
OC-3
t
Cr-D
Figure 2 on page 6
180
200
450
800
4000
215
230
500
840
4100
250
260
550
900
4200
ps
Clock to Data Delay
FEC (2.7 GHz)
OC-48
t
Cf-D
Figure 2 on page 6
–60
–60
–30
–30
0
0
ps
Input Return Loss 100 kHz–1.5 GHz
1.5 GHz–4.0 GHz
–15
–10
—
—
—
—
dB
dB
Slicing Level Offset
1
(relative to the internally set input
common mode voltage)
V
SLICE
SLICE_LVL = 750 mV to
2.25 V
–15 — 15 mV
Slicing Level Accuracy SLICE_LVL = 750 mV to
2.25 V
–500 — 500 µV
Loss-of-Signal Range
2
(peak-to-peak differential)
V
LOS
LOS_LVL = 1.50 TO 2.50 V
0—40mV
Table 2. DC Characteristics (Continued)
(V
DD
= 2.5 V ±5% for Si5022 or 3.3 V ±5% for Si5023, T
A
= –40 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1. No load on LVTTL outputs.
2. These inputs may be driven differentially or single-endedly. When driven single-endedly, the unused input must be ac
coupled to ground.
