ISL6263CHRZ-T Datasheet ISL6263CHRZ, ISL6263CHRZ-T | P10-P12

FN6745.1

July 8, 2010

Static Regulation

The output voltage V

OUT

will be regulated to the value set

by the VID inputs per Table 1. A true differential amplifier

connected to the VSEN and RTN pins implements processor

Kelvin sense for precise core voltage regulation at the GPU

voltage sense points.

The ISL6263C can accommodate DCR current sense or

discrete resistor current sense. The DCR current sense uses

the intrinsic series resistance of the output inductor, as

shown in the application circuit of Figure 2. The discrete

resistor current sense uses a shunt resistor in series with the

output inductor, as shown in the application circuit in

Figure 3. In both cases, the signal is fed to the non-inverting

input of the current sense amplifier at the ISP pin, where it is

measured differentially with respect to the output voltage of

the converter at the VO pin and amplified. The voltage at the

ICOMP pin minus the output voltage measured at the VO

pin, is proportional to the total inductor current. This

information is used for overcurrent protection and current

monitoring. It is important to note that this current

measurement should not be confused with the synthetic

current ripple information created within the R

modulator.

When using inductor DCR current sense, an NTC

compensation network is optional to compensate the

positive temperature coefficient of the copper winding, thus

maintaining the current sense accuracy.

Processor Kelvin Voltage Sense

The remote voltage sense input pins VSEN and RTN of the

ISL6263C are to be terminated at the die of the GPU. Kelvin

sense allows the voltage regulator to tightly control the

processor voltage at the die, compensating for various

resistive voltage drops in the power delivery path.

Since the voltage feedback is sensed at the processor die,

removing the GPU will open the voltage feedback path of the

regulator, causing the output voltage to rise towards VIN.

The ISL6263C will shut down when the voltage between the

VO and VSS pins exceeds the severe overvoltage protection

threshold V

OVPS

of 1.55V. To prevent this issue from

occurring, it is recommended to install resistors R

OPN1

and

OPN2

, as shown in Figure 5. These resistors provide

voltage feedback from the regulator local output in the

absence of the GPU. These resistors should be in the range

of 20Ω to 100Ω

VR_ON

SOFT

OUT

PGOOD

13 SWITCHING CYCLES

~100µs

90%

FIGURE 4. ISL6263C START-UP TIMING

FIGURE 5. SIMPLIFIED GPU KELVIN SENSE AND INDUCTOR DCR CURRENT SENSE

ISP

ISN













VSEN

RTN





VDIFF

OCP

OCSET

ICOMP

Isense

OCSET

IS1

IS2

OUT

NTCS

ESR

NTC

DCR

PHASE

OUT

GND

PROCESSOR

KELVIN

CONNECTIONS

OPN1

OPN2

FILTER1

FILTER2

FILTER1

FILTER2

FILTER3



VDD

10µA

ISL6263C

FN6745.1

July 8, 2010

High Efficiency Diode Emulation Mode

The ISL6263C operates in continuous-conduction-mode

(CCM) during heavy load for minimum conduction loss by

forcing the low-side MOSFET to operate as a synchronous

rectifier. An improvement in light-load efficiency is achieved

by allowing the converter to operate in diode-emulation

mode (DEM) where the low-side MOSFET behaves as a

smart-diode, forcing the device to block negative inductor

current flow.

Positive-going inductor current flows from either the source

of the high-side MOSFET, or the drain of the low-side

MOSFET. Negative-going inductor current flows into the

source of the high-side MOSFET, or into the drain of the

low-side MOSFET. When the low-side MOSFET conducts

positive inductor current, the phase voltage will be negative

with respect to the VSS pin. Conversely, when the low-side

MOSFET conducts negative inductor current, the phase

voltage will be positive with respect to the VSS pin. Negative

inductor current occurs when the output DC load current is

less than ½ the inductor ripple current. Sinking negative

inductor current through the low-side MOSFET lowers

efficiency through unnecessary conduction losses. Efficiency

can be further improved with a reduction of unnecessary

switching losses by reducing the PWM frequency. The PWM

frequency can be configured to automatically make a

step-reduction upon entering DEM by forcing a

step-increase of the window voltage V

. The window

voltage can be configured to increase approximately 30%,

50%, or not at all. The characteristic PWM frequency

reduction, coincident with decreasing load, is accelerated by

the step-increase of the window voltage.

The converter will enter DEM after detecting three

consecutive PWM pulses with negative inductor current. The

negative inductor current is detected during the time that the

high-side MOSFET gate driver output UGATE is low, with the

exception of a brief blanking period. The voltage between

the PHASE pin and VSS pin is monitored by a comparator

that latches upon detection of positive phase voltage. The

converter will return to CCM after detecting three

consecutive PWM pulses with positive inductor current.

The inductor current is considered positive if the phase

comparator has not been latched while UGATE is low.

Because the switching frequency in DEM is a function of

load current, very light load condition can produce

frequencies well into the audio band. To eliminate this

audible noise, an audio filter can be enabled that briefly turns

on the low-side MOSFET gate driver LGATE approximately

every 35µs.

The DEM and audio filter operation are programmed by the

AF_EN and FDE pins in conjunction with VID0:VID4

according to Table 2.

Smooth mode transitions are facilitated by the R

modulator,

which correctly maintains the internally synthesized ripple

current information throughout mode transitions.

Current Monitor

The ISL6263C features a current monitor output. The

voltage between the IMON and VSS pins is proportional to

the output inductor current. The output inductor current is

proportional to the voltage between the ICOMP and VO pins.

The IMON pin has source and sink capability for close

tracking of transient current events. The current monitor

output is expressed in Equation 1:

Protection

The ISL6263C provides overcurrent protection (OCP),

overvoltage protection (OVP), and undervoltage protection

(UVP), as shown in Table 3.

Overcurrent protection is tied to the current sense amplifier.

Given the overcurrent set point I

, the maximum voltage

at ICOMP pin V

ICOMP(max)

(which is the voltage when

OCP happens) can be determined by the current sense

network (explained in “Inductor DCR Current Sense” on

page 14 and “Resistor Current Sense” on page 15). During

start-up, the ICOMP pin must fall 25mV below the OCSET

pin to reset the overcurrent comparator, which requires

ICOMP(max)

- V

) > 25mV.

The OCP threshold detector is checked every 15µs and will

increment a counter if the OCP threshold is exceeded,

conversely the counter will be decremented if the load

current is below the OCP threshold. The counter will latch an

OCP fault when the counter reaches eight. The fastest OCP

response for overcurrent levels that are no more than 2.5

times the OCP threshold is 120µs, which is eight counts at

15µs each. The ISL6263C protects against hard shorts by

latching an OCP fault within 2µs for overcurrent levels

exceeding 2.5 times the OCP threshold.

The overcurrent threshold is determined by the resistor

OCSET

between OCSET pin and VO pin. The value of

OCSET

is calculated in Equation 2:

TABLE 2. DIODE EMULATION MODE and AUDIO FILTER

GPU MODE

(VID code) FDE AF_EN

DEM

STATUS

VOLTAGE

WINDOW

AUDIO

FILTER

MODE 1

DISABLED

NOM -

ENABLED

130% NOM -

MODE 2

-0

ENABLED

150% NOM

ENABLED

130% NOM

ENABLED

130% NOM

ENABLED

IMON

ICOMP

–31=

(EQ. 1)

OCSET

ICOMP max

–

10A

----------------------------------------------------

(EQ. 2)

ISL6263C

FN6745.1

July 8, 2010

For example, choose V

ICOMP(max)

- V

= 80mV. R

OCSET

can use a 8.06kΩresistor, according to Equation 2.

UVP and OVP are independent of the OCP. If the output

voltage measured on the VO pin is less than +300mV below

the voltage on the SOFT pin for longer than 1ms, the

controller will latch a UVP fault. If the output voltage

measured on the VO pin is >195mV above the voltage on

the SOFT pin for longer than 1ms, the controller will latch an

OVP fault. Keep in mind that V

SOFT

will equal the voltage

level commanded by the VID states only after the soft-start

capacitor C

SOFT

has slewed to the VID DAC output voltage.

The UVP and OVP detection circuits act on static and

dynamic V

SOFT

voltage.

When an OCP, OVP, or UVP fault has been latched, PGOOD

becomes a low impedance and the gate driver outputs

UGATE and LGATE are pulled low. The energy stored in the

inductor is dissipated as current flows through the low-side

MOSFET body diode. The controller will remain latched in

the fault state until the VR_ON pin has been pulled below the

falling VR_ON threshold voltage V

VR_ONL

or until VDD has

gone below the falling POR threshold voltage

VDD_THF

A severe-overvoltage protection fault occurs immediately after

the voltage between the VO and VSS pins exceed the rising

severe-overvoltage threshold V

OVPS

which is 1.545V, the

same reference voltage used by the VID DAC. The ISL6263C

will latch UGATE and PGOOD low but unlike other protective

faults, LGATE remains high until the voltage between VO and

VSS falls below approximately 0.77V, at which time LGATE is

pulled low. The LGATE pin will continue to switch high and low

at 1.545V and 0.77V until VDD has gone below the falling

POR threshold voltage

VDD_THF.

This provides maximum

protection against a shorted high-side MOSFET while

preventing the output voltage from ringing below ground. The

severe-overvoltage fault circuit can be triggered after another

fault has already been latched.

Gate-Driver Outputs LGATE and UGATE

The ISL6263C has internal high-side and low-side

N-Channel MOSFET gate-drivers. The LGATE driver is

optimized for low duty-cycle applications where the low-side

MOSFET conduction losses are dominant. The LGATE

pull-down resistance is very low in order to clamp the

gate-source voltage of the MOSFET below the V

GS(th)

turn-off. The current transient through the low-side gate at

turn-off can be considerable due to the characteristic large

switching charge of a low r

DS(ON)

MOSFET.

Adaptive shoot-through protection prevents the gate-driver

outputs from going high until the opposite gate-driver output

has fallen below approximately 1V. The UGATE turn-on

propagation delay t

PDRU

and LGATE turn-on propagation

delay t

PDRL

are found in the “Electrical Specifications” table

on page 6. The power for the LGATE gate-driver is sourced

directly from the PVCC pin. The power for the UGATE

gate-driver is sourced from a boot-strap capacitor connected

across the BOOT and PHASE pins. The boot capacitor is

charged from PVCC through an internal boot-strap diode

each time the low-side MOSFET turns on, pulling the

PHASE pin low.

TABLE 3. FAULT PROTECTION SUMMARY OF

ISL6263C

FAULT TYPE

FAULT

DURATION

PRIOR TO

PROTECTION

ACTIONS

FAULT

RESET

Overcurrent 120µs LGATE, UGATE, and

PGOOD latched low

Cycle

VR_ON or

VDD

Short Circuit <2µs LGATE, UGATE, and

PGOOD latched low

Cycle

VR_ON or

VDD

Overvoltage

(+195mV)

between VO pin

and SOFT pin

1ms LGATE, UGATE, and

PGOOD latched low

Cycle

VR_ON or

VDD

Severe

Overvoltage

(+1.55V)

between VO pin

and VSS pin

Immediately UGATE, and

PGOOD latched low,

LGATE toggles ON

when VO > 1.55V

OFF when

VO < 0.77V

until fault reset

Cycle

VDD only

Undervoltage

(-300mV)

between VO pin

and SOFT pin

1ms LGATE, UGATE, and

PGOOD latched low

Cycle

VR_ON or

VDD

TABLE 3. FAULT PROTECTION SUMMARY OF

ISL6263C (Continued)

FAULT TYPE

FAULT

DURATION

PRIOR TO

PROTECTION

ACTIONS

FAULT

RESET

PWM

UGATE

PDRL

PDRU

LGATE

FIGURE 6. GATE DRIVER TIMING DIAGRAM

ISL6263C

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18

ISL6263CHRZ-T

Mfr. #:

Buy ISL6263CHRZ-T

Manufacturer:

Renesas / Intersil

Description:

Voltage Regulators - Switching Regulators 1-PHS INT DC/DC BUCK CNTRLR IMVP-6 W/IMON

Lifecycle:

New from this manufacturer.

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ISL6263CHRZ-T

ISL6263CHRZ-T

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