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ISL6263CHRZ-T

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
7
FN6745.1
July 8, 2010
POWER GOOD and PROTECTION MONITOR
PGOOD Low Voltage V
PGOOD
I
PGOOD
= 4mA 0.11 0.40 V
PGOOD Leakage Current I
PGOOD
V
PGOOD
= 3.3V -1.0 1.0 µA
Overvoltage Threshold (VO-VSOFT) V
OVP
V
O
rising above V
SOFT
> 1ms 155 195 235 mV
Severe Overvoltage Threshold V
OVPS
V
O
rising above 1.55V reference > 0.5µs 1.525 1.550 1.575 V
OCSET Reference Current I
OCSET
R
RBIAS
= 150kΩ 9.9 10.1 10.3 µA
OCSET Voltage Threshold Offset V
OCSET_OFS
V
ICOMP
rising above V
OCSET
> 120µs -3 3 mV
Undervoltage Threshold (VSOFT-VO) V
UVF
V
O
falling below V
SOFT
for > 1ms -360 -300 -240 mV
CONTROL INPUTS
VR_ON Input Low V
VR_ONL
1 V
VR_ON Input High V
VR_ONH
2.3 V
AF_EN Input Low V
AF_ENL
1 V
AF_EN Input High V
AF_ENH
2.3 V
VR_ON Leakage I
VR_ONL
V
VR_ON
= 0V -1.0 0µA
I
VR_ONH
V
VR_ON
= 3.3V 0 1.0 µA
AF_EN Leakage I
AF_ENL
V
AF_EN
= 0V -1.0 0µA
I
AF_ENH
V
AF_EN
= 3.3V 0.45 1.0 µA
VID<4:0> Input Low V
VIDL
0.4 V
VID<4:0> Input High V
VIDH
0.7 V
FDE Input Low V
FDEL
0.3 V
FDE Input High V
FDEH
0.7 V
VID<4:0> Leakage I
VIDL
V
VID
= 0V -1.0 0µA
I
VIDH
V
VID
= 1.0V 0.45 1.0 µA
FDE Leakage I
FDEL
V
FDE
= 0V -1.0 0µA
I
FDEH
V
FDE
= 1.0V 0.45 1.0 µA
NOTES:
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
7. Limits established by characterization and are not production tested.
Electrical Specifications These specifications apply for T
A
= -10°C to +100°C, unless otherwise stated.
All typical specifications T
A
= +25°C, V
DD
= 5V, PVCC = 5V. Boldface limits apply over the operating
temperature range, -10°C to +100°C. (Continued)
PARAMETER SYMBOL TEST CONDITIONS
MIN
(Note 6) TYP
MAX
(Note 6) UNITS
ISL6263C
8
FN6745.1
July 8, 2010
Functional Pin Descriptions
RBIAS (Pin 1) - Sets the internal 10µA current reference.
Connect a 150kΩ±1resistor from RBIAS to VSS.
SOFT (Pin 2) - Sets the output voltage slew-rate. Connect
an X5R or X7R ceramic capacitor from SOFT to VSS. The
SOFT pin is the non-inverting input of the error amplifier.
OCSET (Pin 3) - Sets the overcurrent threshold. Connect a
resistor from OCSET to VO.
VW (Pin 4) - Sets the static PWM switching frequency in
continuous conduction mode. Connect a resistor from VW to
COMP.
COMP (Pin 5) - Connects to the output of the control loop
error amplifier.
FB (Pin 6) - Connects to the inverting input of the control
loop error amplifier.
VDIFF (Pin 7) - Connects to the output of the VDIFF
differential amplifier. Together with the FB pin, it is used for
the output voltage feedback.
VSEN (Pin 8) - This is the V
OUT
input of the GPU processor
Kelvin connection. Connects internally to the non-inverting
inputs of the VDIFF differential amplifier.
RTN (Pin 9) - This is the V
GND
input of the GPU processor
Kelvin connection. Connects internally to the inverting inputs
of the VDIFF differential amplifier.
ICOMP (Pin 10) - Connects to the output of the differential
current sense amplifier and to the non-inverting inputs of the
overcurrent comparator. Used for output current monitor and
overcurrent protection.
ISN (Pin 11) - This is the feedback of the current sense
amplifier. Connects internally to the inverting input of the
current sense amplifier. Used for output current sense.
VO (Pin 12) - Connects to the inverting inputs of the VDIFF
differential amplifier.
ISP (Pin 13) - Connects to the non-inverting input of the
current sense amplifier. Used for output current sense.
VIN (Pin 14) - Connects to the R
3
PWM modulator providing
input voltage feed-forward. For optimum input voltage
transient response, connect near the drain of the high-side
MOSFETs.
VSS (Pin 15) - Analog ground.
VDD (Pin 16) - Input power supply for the IC. Connect to
+5VDC and decouple with at least a 1µF MLCC capacitor
from the VDD pin to the VSS pin.
BOOT (Pin 17) - Input power supply for the high-side
MOSFET gate driver. Connect an MLCC bootstrap capacitor
from the BOOT pin to the PHASE pin.
UGATE (Pin 18) - High-side MOSFET gate driver output.
Connect to the gate of the high-side MOSFET.
PHASE (Pin 19) - Current return path for the UGATE
high-side MOSFET gate driver. Detects the polarity of the
PHASE node voltage for diode emulation. Connect the
PHASE pin to the drains of the low-side MOSFETs.
PGND (Pin 20) - Current return path for the LGATE low-side
MOSFET gate driver. The PGND pin only conducts current
when LGATE pulls down. Connect the PGND pin to the
sources of the low-side MOSFETs.
LGATE (Pin 21) - Low-side MOSFET gate driver output.
Connect to the gate of the low-side MOSFET.
PVCC (Pin 22) - Input power supply for the low-side
MOSFET gate driver, and the high-side MOSFET gate
driver, via the internal bootstrap diode connected between
the PVCC and BOOT pins. Connect to +5VDC and decouple
with at least 1µF of an MLCC capacitor from the PVCC pin to
the PGND pin.
VID0:VID4 (Pin 23:Pin 27) - Voltage identification inputs.
VID0 input is the least significant bit (LSB) and VID4 input is
the most significant bit (MSB).
IMON (Pin 28) - A voltage signal proportional to the output
current of the converter.
VR_ON (Pin 29) - A high logic signal on this pin enables the
converter and a low logic signal disables the converter.
AF_EN (Pin 30) - Used in conjunction with VID0:VID4 and
FDE pins to program the diode-emulation and audio filter
behavior. Refer to Table 2.
PGOOD (Pin 31) - The PGOOD pin is an open-drain output
that indicates when the converter is able to supply regulated
voltage. Connect the PGOOD pin to a maximum of 5V
through a pull-up resistor.
FDE (Pin 32) - Used in conjunction with VID0:VID4 and
AF_EN pins to program the diode-emulation and audio filter
behavior. Refer to Table 2.
BOTTOM - Connects to substrate. Electrically isolated but
should be connected to VSS. Requires best practical
thermal coupling to PCB.
ISL6263C
9
FN6745.1
July 8, 2010
Theory of Operation
The R
3
Modulator
The heart of the ISL6263C is Intersil’s Robust-Ripple-
Regulator (R
3
) Technology™. The R
3
modulator is a hybrid
of fixed frequency PWM control, and variable frequency
hysteretic control that will simultaneously affect the PWM
switching frequency and PWM duty cycle in response to
input voltage and output load transients.
The term “Ripple” in the name “Robust-Ripple-Regulator”
refers to the synthesized voltage-ripple signal V
R
that
appears across the internal ripple-capacitor C
R.
The V
R
signal is a representation of the output inductor ripple
current. Transconductance amplifiers measuring the input
voltage of the converter and the output set-point voltage
V
SOFT
, together produce the voltage-ripple signal V
R
.
A voltage window signal V
W
is created across the VW and
COMP pins by sourcing a current proportional to g
m
V
SOFT
through a parallel network consisting of resistor R
FSET
and
capacitor C
FSET.
The synthesized voltage-ripple signal V
R
along with similar companion signals are converted into
PWM pulses.
The PWM frequency is proportional to the difference in
amplitude between V
W
and V
COMP
. Operating on these
large-amplitude, low noise synthesized signals allows the
ISL6263C to achieve lower output ripple and lower phase
jitter than either conventional hysteretic or fixed frequency
PWM controllers. Unlike conventional hysteretic converters,
the ISL6263C has an error amplifier that allows the controller
to maintain tight voltage regulation accuracy throughout the
VID range from 0.41200V to 1.28750V.
Voltage Programming
The output voltage V
OUT
is regulated to the SOFT pin
voltage, V
SOFT
, which is determined by the DAC output. The
DAC output voltage is programmed by the external five VID
pins. Refer to Table 1 for the VID voltage programming
specification.
Power-On Reset
The ISL6263C is disabled until the voltage at the VDD pin
has increased above the rising VDD power-on reset (POR)
V
DD_THR
threshold voltage. The controller will become
disabled when the voltage at the VDD pin decreases below
the falling POR V
DD_THF
threshold voltage.
Start-Up Timing
Figure 4 shows the ISL6263C start-up timing. Once VDD
has ramped above V
DD_THR
, the controller can be enabled
by pulling the VR_ON pin voltage above the input-high
threshold V
VR_ONH
. Approximately 100µs later, the soft-start
capacitor C
SOFT
begins slewing to the designated VID
set-point as it is charged by the soft-start current source I
SS
.
The V
OUT
output voltage of the converter follows the V
SOFT
voltage ramp to within 10% of the VID set-point then counts
13 switching cycles, then changes the open-drain output of
the PGOOD pin to high impedance. During soft-start, the
regulator always operates in continuous conduction mode
(CCM).
TABLE 1. VID AND DAC TRUTH TABLE
GPU
MODE VID4 VID3 VID2 VID1 VID0
V
SOFT
(DAC) (V)
GPU MODE 1
----- 0
0 0 0 0 0 1.28750
0 0 0 0 1 1.26175
0 0 0 1 0 1.23600
0 0 0 1 1 1.21025
0 0 1 0 0 1.18450
0 0 1 0 1 1.15875
0 0 1 1 0 1.13300
0 0 1 1 1 1.10725
0 1 0 0 0 1.08150
0 1 0 0 1 1.05575
0 1 0 1 0 1.03000
0 1 0 1 1 1.00425
0 1 1 0 0 0.97850
0 1 1 0 1 0.95275
0 1 1 1 0 0.92700
0 1 1 1 1 0.90125
1 0 0 0 0 0.87550
1 0 0 0 1 0.84975
GPU MODE 2
1 0 0 1 0 0.82400
1 0 0 1 1 0.79825
1 0 1 0 0 0.77250
1 0 1 0 1 0.74675
1 0 1 1 0 0.72100
1 0 1 1 1 0.69525
1 1 0 0 0 0.66950
1 1 0 0 1 0.64375
1 1 0 1 0 0.61800
1 1 0 1 1 0.59225
1 1 1 0 0 0.56650
1 1 1 0 1 0.54075
1 1 1 1 0 0.51500
1 1 1 1 1 0.41200
ISL6263C
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

ISL6263CHRZ-T

Mfr. #:
Buy ISL6263CHRZ-T
Manufacturer:
Renesas / Intersil
Description:
Voltage Regulators - Switching Regulators 1-PHS INT DC/DC BUCK CNTRLR IMVP-6 W/IMON
Lifecycle:
New from this manufacturer.
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