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ISL6263CHRZ-T

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
13
FN6745.1
July 8, 2010
Internal Bootstrap Diode
The ISL6263C has an integrated boot-strap Schottky diode
connected from the PVCC pin to the BOOT pin. Simply
adding an external capacitor across the BOOT and PHASE
pins completes the bootstrap circuit.
The minimum value of the bootstrap capacitor can be
calculated using Equation 3:
where Q
GATE
is the amount of gate charge required to fully
charge the gate of the upper MOSFET. The V
BOOT
term is
defined as the allowable droop in the rail of the upper drive.
As an example, suppose an upper MOSFET has a gate
charge, Q
GATE
, of 25nC at 5V and also assume the droop in
the drive voltage at the end of a PWM cycle is 200mV. One
will find that a bootstrap capacitance of at least 0.125µF is
required. The next larger standard value capacitance is
0.15µF. A good quality ceramic capacitor is recommended.
Soft-Start and Soft Dynamic VID Slew Rates
The output voltage of the converter tracks V
SOFT,
the
voltage across the SOFT and VSS pins. Shown in Figure 1,
the SOFT pin is connected to the output of the VID DAC
through the unidirectional soft-start current source I
SS
or the
bidirectional soft-dynamic VID current source I
DVID
, and the
non-inverting input of the error amplifier. Current is sourced
from the SOFT pin when I
SS
is active. The SOFT pin can
both source and sink current when I
DVID
is active. The
soft-start capacitor C
SOFT
changes voltage at a rate
proportional to I
SS
or I
DVID
. The ISL6263C automatically
selects I
SS
for the soft-start sequence so that the inrush
current through the output capacitors is maintained below
the OCP threshold. Once soft-start has completed, I
DVID
is
automatically selected for output voltage changes
commanded by the VID inputs, charging C
SOFT
when the
output voltage is commanded to rise, and discharging
C
SOFT
when the output voltage is commanded to fall.
The GPU voltage regulator may require a minimum voltage
slew rate, which will be guaranteed by the value of C
SOFT
.
For example, if the regulator requires 10mV/µs slew rate, the
value of C
SOFT
can be calculated using Equation 4:
I
DVID
is the soft-dynamic VID current source, and its
minimum value is specified in the “Electrical Specifications”
table on page 5. Choosing the next lower standard
component value of 0.015µF will guarantee 10mV/µs slew
rate. This choice of C
SOFT
controls the startup slew-rate as
well. One should expect the output voltage during soft-start
to slew to the voltage commanded by the VID settings at a
nominal rate given by Equation 5:
Note that the slew rate is the average rate of change
between the initial and final voltage values.
It is worth it to mention that the surge current charges the
output capacitors when the output voltage is commanded to
rise. This surge current could be high enough to trigger the
OC protection circuit if the voltage slew rate is too high,
or/and the output capacitance is too large. The overcurrent
set point should guarantee the VID code transition
successful.
RBIAS Current Reference
The RBIAS pin is internally connected to a 1.545V reference
through a 3kΩ resistance. A bias current is established by
connecting a±1% tolerance, 150kΩ resistor between the
RBIAS and VSS pins. This bias current is mirrored, creating the
reference current I
OCSET
that is sourced from the OCSET pin.
Do not connect any other components to this pin, as they will
have a negative impact on the performance of the IC.
Setting the PWM Switching Frequency
The R
3
modulator scheme is not a fixed-frequency
architecture, lacking a fixed-frequency clock signal to
produce PWM. The switching frequency increases during
the application of a load to improve transient performance.
The static PWM frequency varies slightly depending on the
input voltage, output voltage, and output current, but this
variation is normally less than 10% in continuous conduction
mode.
Refer to Figure 2 and find that resistor R
FSET
is connected
between the V W and COMP pins. A current is sourced from
VW through R
FSET
creating the synthetic ripple window
voltage signal V
W
, which determines the PWM switching
frequency. The relationship between the resistance of R
FSET
FIGURE 7. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE
VOLTAGE
20nC
V
BOOT_CAP
(V)
C
BOOT_CAP
(µF)
2.0
1.6
1.4
1.0
0.8
0.6
0.4
0.2
0.0
0.30.0 0.1 0.2 0.4 0.5 0.6 0.90.7 0.8 1.0
Q
GATE
= 100nC
1.2
1.8
50
n
C
C
BOOT
Q
GATE
V
BOOT
------------------------
(EQ. 3)
dV
SOFT
dt
-----------------------
I
SS
C
SOFT
-------------------
42A
0.015F
-----------------------
==
2.8mV
s
------------------
(EQ. 5)
ISL6263C
14
FN6745.1
July 8, 2010
and the switching frequency in CCM is approximated using
Equation 6:
t is the switching period. For example, the value of R
FSET
for
300kHz operation is approximated using Equation 7:
This relationship only applies to operation in constant
conduction mode because the PWM frequency naturally
decreases as the load decreases while in diode emulation
mode.
Inductor DCR Current Sense
ISL6263C provides the option of using the inductor DCR for
current sense. To maintain the current sense accuracy, an
NTC compensation network is optional when using DCR
sense. The process to compensate the DCR resistance
variation takes several iterative steps. Figure 2 shows the
DCR sense method. Figure 8 shows the simplified model of
the current sense circuitry. The inductor DC current I
O
generates a DC voltage drop on the inductor DCR.
Equation 8 gives this relationship:
An R-C network senses the voltage across the inductor to
get the inductor current information. R
N
represents the
equivalent resistance of R
P
and the optional NTC network
consisting of R
NTC
and R
NTCS
. R
N
is temperature T
dependent and is given by Equation 9:
If the NTC network is not used, simply set R
N
(T) = R
P
.
Sensing the time varying inductor current accurately
requires that the parallel R-C network time constant match
the inductor L/DCR time constant. Equation 10 shows this
relationship:
Solution of C
N
yields:
The first step is to adjust R
N
(T) and R
S
such that the correct
current information appears between the ISP and VO pins
even at light loads. Assume V
N
is the voltage drop across
R
N
(T). The V
N
to V
DCR
gain G
1
(T) provides a reasonable
amount of light load signal from which to derive the current
information. G
1
(T) is given by Equation 12:
The gain of the current sense amplifier circuit is expressed in
Equation 13:
The current sense amplifier output voltage is given by
Equation 14:
The inductor DCR is a function of temperature T and is
approximated using Equation 15:
R
FSET
t0.510
6–
–
400 10
12–
---------------------------------------
=
(EQ. 6)
7.1
3
10
3.33 10
6–
0.5 10
6–
–
400 10
12–
--------------------------------------------------------------------
=
(EQ. 7)
V
DCR
I
O
DCR=
(EQ. 8)
FIGURE 8. EQUIVALENT MODEL OF CURRENT SENSE USING INDUCTOR DCR CURRENT SENSE
ISP
ISN
VO
OCP
OCSET
ICOMP
I
SENSE
R
OCSET
R
IS1
R
IS2
VDD
10µA
C
N
R
S
R
N
V
DCR
V
N
+
-
R
N
T
R
NTC
R
NTCS
+R
P
R
NTC
R
NTCS
R
P
++
------------------------------------------------------------
=
(EQ. 9)
K
ISENSE
1
R
IS2
R
IS1
-------------
+=
(EQ. 13)
V
ICOMP
V
O
V
N
+ K
ISENSE
=
(EQ. 14)
DCR T DCR +25C1 0.00393 T +25C–+=
(EQ. 15)
ISL6263C
15
FN6745.1
July 8, 2010
0.00393 is the temperature coefficient of the copper. To
make V
ICOMP
independent of the inductor temperature, the
NTC characteristic is desired to satisfy:
where G
1target
is the desired ratio of V
N
/V
DCR
. Therefore,
the temperature characteristics G
1
, which determines
parameters selection, is described by Equation 17:
It is recommended to begin the DCR current sense design
using the R
NTC
, R
NTCS
, and R
P
component values of the
evaluation board available from Intersil.
Given the inductor DCR and the overcurrent set point I
OC
, the
maximum voltage of ICOMP pin is determined by
Equation 18:
R
N
, R
S
, R
IS1
, R
IS2
should be adjusted to meet the
requirement (V
ICOMP(max)
- V
O
) > 25mV and the time
constant matching according to Equation 10.
The effectiveness of the R
N
network is sensitive to the
coupling coefficient between the NTC thermistor and the
inductor. The NTC thermistor should be placed in the closet
proximity of the inductor.
Resistor Current Sense
Figure 3 shows a detailed schematic using discrete resistor
sense of the inductor current. Figure 9 shows the equivalent
circuit. Since the current sense resistor voltage represents
the actual inductor current information, R
S
and C
N
simply
provide noise filtering. A low ESL sense resistor is strongly
recommended for R
SNS
because this parameter is the most
significant source of noise that affects discrete resistor
sense. It is recommended to start out using 100Ω for R
S
and
47pF for C
N
. Since the current sense resistance changes
very little with temperature, the NTC network is not needed
for thermal compensation. Discrete resistor sense design
follows the same approach as DCR sense. The voltage on
the current sense resistor is given by Equation 19:
It is optional to parallel a resistor R
P
to form a voltage divider
with R
S
to obtain more flexibility. Assume the voltage across
R
P
is V
N
, which is given by Equation 20:
The current sense amplifier output voltage V
ICOMP
is given
by Equation 21:
Given an current sense resistor R
SNS
and the overcurrent set
point I
OC
, the maximum voltage of ICOMP pin is determined
by Equation 22:
If R
P
is not used, the maximum voltage of ICOMP pin is
determined by Equation 23:
R
S
, R
P
, R
IS1
, R
IS2
should be adjusted to meet the
requirement (V
ICOMP(max)
- V
O
) > 25mV.
The current sense traces should be routed directly to the
current sense resistor pads for accurate measurement.
However, due to layout imperfection, the calculated R
IS2
may still need slight adjustment to achieve optimum load line
slope. It is recommended to adjust R
IS2
after the system has
achieved thermal equilibrium at full load.
G
1
T 1 0.00393 T +25C–+ G
1t etarg
(EQ. 16)
G
1
T
G
1t etarg
1 0.00393 T +25C–+
-------------------------------------------------------------------------
=
(EQ. 17)
V
ICOMP max
V
O
– I
OC
DCR 25C
R
N
+25C
R
N
+25CR
S
+
----------------------------------------------
1
R
IS2
R
IS1
-------------
+



 =
(EQ. 18)
FIGURE 9. EQUIVALENT MODEL OF CURRENT SENSE USING DISCRETE RESISTOR CURRENT SENSE
ISP
ISN
VO
OCP
OCSET
ICOMP
I
SENSE
R
OCSET
R
IS1
R
IS2
VDD
10µA
C
N
R
S
V
RSNS
R
P
(OPTIONAL)
V
N
-
+
V
ICOMP max
V
O
– I
OC
R
SNS
R
P
R
S
R
P
+
----------------------
1
R
IS2
R
IS1
-------------
+



 =
(EQ. 22)
V
ICOMP max
V
O
– I
OC
R
SNS
1
R
IS2
R
IS1
-------------
+



=
(EQ. 23)
ISL6263C
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

ISL6263CHRZ-T

Mfr. #:
Buy ISL6263CHRZ-T
Manufacturer:
Renesas / Intersil
Description:
Voltage Regulators - Switching Regulators 1-PHS INT DC/DC BUCK CNTRLR IMVP-6 W/IMON
Lifecycle:
New from this manufacturer.
Delivery:
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