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87604AGILFT

P1-P3P4-P6P7-P9P10-P12P13-P13
Low Voltage/Low Skew, 1:4 PCI/PCI-X
Zero Delay Clock Generator
87604I
DATA SHEET
87604I REVISION B 11/11/15 1 ©2015 Integrated Device Technology, Inc.
GENERAL DESCRIPTION
The 87604I is a 1:4 PCI/PCI-X Clock Generator. The 87604I has
a selectable REF_IN or crystal input. The REF_IN input accepts
LVCMOS or LVTTL input levels. The 87604I has a fully integrated
PLL along with frequency confi gurable clock and feedback outputs
for multiply-ing and regenerating clocks with “zero delay”. The
PLL’s VCO has an operating range of 250MHz - 500MHz, allowing
this device to be used in a variety of general purpose clocking
applications. For PCI/PCI-X applications in particular, the VCO
frequency should be set to 400MHz. This can be accomplished
by supplying 33.33MHz, 25MHz, 20MHz, or 16.66MHz on the
reference clock or crystal input and by selecting ÷12, ÷16, ÷20, or
÷24, respectively as the feedback divide value. The divider on the
output bank can then be confi gured to generate 33.33MHz (÷12),
66.66MHz (÷6), 100MHz (÷4), or 133.33MHz (÷3).
The 87604I is characterized to operate with its core
supply at 3.3V and the bank supply at 3.3V or 2.5V. The
87604I is packaged in a small 6.1mm x 9.7mm TSSOP
body, making it ideal for use in space-constrained applications.
FEATURES
• Fully integrated PLL
• Four LVCMOS/LVTTL outputs, 15Ω typical output impedance
• Selectable crystal oscillator interface or
LVCMOS/LVTTL REF_IN clock input
• Maximum output frequency: 166.67MHz
• Maximum crystal input frequency: 38MHz
• Maximum REF_IN input frequency: 41.67MHz
• Individual banks with selectable output dividers for
generating 33.333MHz, 66.66MHz, 100MHz and
133.333MHz
• Separate feedback control for generating PCI / PCI-X
frequencies from a 16.66MHz or 20MHz crystal, or 25MHz
or 33.33MHz reference frequency
• VCO range: 250MHz to 500MHz
• Cycle-to-cycle jitter: 120ps (maximum)
• Period jitter, RMS: 20ps (maximum)
• Output skew: 65ps (maximum)
• Static phase offset: 160ps ± 160ps
• Voltage Supply Modes:
V
DD
/V
DDA
/V
DDO
3.3/3.3/3.3
3.3/3.3/2.5
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
PIN ASSIGNMENT
87604I
28-Lead TSSOP, 240MIL
6.1mm x 9.7mm x 0.92mm
body package
G Package
Top View
VDD
FB_IN
GND
FB_OUT
REF_OUT
V
DDO
Q3
Q2
GND
Q1
Q0
V
DDO
PLL_SEL
V
DDA
FBDIV_SEL1
FBDIV_SEL0
DIV_SEL1
DIV_SEL0
nc
MR
nc
GND
GND
nc
REF_IN
XTAL_OUT
XTAL_IN
XTAL_SEL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
BLOCK DIAGRAM
Low Voltage/Low Skew, 1:4 PCI/PCI-X
Zero Delay Clock Generator
87604I DATA SHEET
2 REVISION B 11/11/15
TABLE 1. PIN DESCRIPTIONS
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 4 pF
R
PULLUP
Input Pullup Resistor 51 kΩ
R
PULLDOWN
Input Pulldown Resistor 51 kΩ
C
PD
Power Dissipation Capacitance
(per output); NOTE 1
V
DD
, V
DDA
, V
DDO
= 3.465V 9 pF
V
DD
, V
DDA
= 3.465V; V
DDO
= 2.625V 11 pF
R
OUT
Output Impedance 15
Ω
Number Name Type Description
1V
DD
Power Core supply pin.
2 FB_IN Input Pulldown
Feedback input to phase detector for generating clocks with
“zero delay”. LVCMOS / LVTTL interface levels.
3, 9, 20, 21 GND Power Power supply ground.
4 FB_OUT Output Feedback output. Connect to FB_IN. LVCMOS / LVTTL interface levels.
5 REF_OUT Output Reference clock output. LVCMOS / LVTTL interface levels.
6, 12 V
DDO
Power Output supply pin
7, 8,
10, 11
Q3, Q2,
Q1, Q0
Output
Clock outputs. 15
Ω typical output impedance.
LVCMOS / LVTTL interface levels.
13 PLL_SEL Input Pullup
Selects between PLL and bypass mode. When HIGH, selects PLL.
When LOW, selects reference clock. LVCMOS / LVTTL interface levels.
14 V
DDA
Power Analog supply pin. See Applications Note for fi ltering.
15 XTAL_SEL Input Pullup
Selects between crystal oscillator or reference clock as the PLL reference
source. Selects XTAL inputs when HIGH. Selects REF_IN when LOW.
LVCMOS / LVTTL interface levels.
16,
17
XTAL_IN,
XTAL_OUT
Input
Crystal oscillator interface. XTAL_IN is the input.
XTAL_OUT is the output.
18 REF_IN Input Pulldown Reference clock input. LVCMOS / LVTTL interface levels.
19, 22, 24 nc Unused No connect.
23 MR Input Pulldown
Active HIGH Master Reset. When logic HIGH, the internal dividers
are reset causing the outputs go low. When logic LOW, the internal divid-
ers and the outputs are enabled. LVCMOS / LVTTL interface levels.
25,
26
DIV_SEL0,
DIV_SEL1
Input Pulldown
Selects divide value for clock outputs as described in Table 3.
LVCMOS / LVTTL interface levels.
27,
28
FBDIV_SEL0,
FBDIV_SEL1
Input Pulldown
Selects divide value for reference clock output and feedback output.
LVCMOS / LVTTL interface levels.
NOTE:
Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
REVISION B 11/11/15
87604I DATA SHEET
3 Low Voltage/Low Skew, 1:4 PCI/PCI-X
Zero Delay Clock Generator
TABLE 3A. OUTPUT CONTROL PIN FUNCTION TABLE
Inputs Outputs
MR Q0:Q3 FB_OUT, REF_OUT
1 LOW LOW
0 Active Active
TABLE 3B. OPERATING MODE FUNCTION TABLE
Inputs
Operating Mode
PLL_SEL
0 Bypass
1 PLL
TABLE 3C. PLL INPUT FUNCTION TABLE
Inputs
XTAL_SEL PLL Input
0 REF_IN
1 XTAL Oscillator
TABLE 3D. CONTROL FUNCTION T ABLE
Inputs
Outputs
PLL_SEL=1 Frequency
FBDIV_SEL1 FBDIV_SEL0 DIV_SEL1 DIV_SEL0
Reference
Frequency
Range (MHz)
Q0:Q3 Q0:Q3 (MHz)
FB_OUT
(MHz)
0 0 0 0 16.67 - 41.67 x 4 66.68 - 166.68 16.67 - 41.67
0 0 0 1 16.67 - 41.67 x 3 50 - 125 16.67 - 41.67
0 0 1 0 16.67 - 41.67 x 2 33.34 - 83.34 16.67 - 41.67
0 0 1 1 16.67 - 41.67 x 1 16.67 - 41.67 16.67 - 41.67
0 1 0 0 12.5 - 31.25 x 5.33 66.63 - 166.56 12.5 - 31.25
0 1 0 1 12.5 - 31.25 x 4 50 - 125 12.5 - 31.25
0 1 1 0 12.5 - 31.25 x 2.667 33.34 - 83.34 12.5 - 31.25
0 1 1 1 12.5 - 31.25 x 1.33 16.63 - 41.56 12.5 - 31.25
1 0 0 0 10 - 25 x 6.667 66.67 - 166.68 10 - 25
1 0 0 1 10 - 25 x 5 50 - 125 10 - 25
1 0 1 0 10 - 25 x 3.33 33.30 - 83.25 10 - 25
1 0 1 1 10 - 25 x 1.66 16.60 - 41.50 10 - 25
1 1 0 0 8.33 - 20.83 x 8 66.64 - 166.64 8.33 - 20.83
1 1 0 1 8.33 - 20.83 x 6 50 - 125 8.33 - 20.83
1 1 1 0 8.33 - 20.83 x 4 33.32 - 83.32 8.33 - 20.83
1 1 1 1 8.33 - 20.83 x 2 16.66 - 41.66 8.33 - 20.83
NOTE: VCO frequency range for all confi gurations above is 250MHz to 500MHz.
P1-P3P4-P6P7-P9P10-P12P13-P13

87604AGILFT

Mfr. #:
Buy 87604AGILFT
Manufacturer:
IDT
Description:
Clock Generators & Support Products 4 LVCMOS OUT CLOCK GEN
Lifecycle:
New from this manufacturer.
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