Low Voltage/Low Skew, 1:4 PCI/PCI-X
Zero Delay Clock Generator
87604I DATA SHEET
10 REVISION B 11/11/15
TRANSISTOR COUNT
The transistor count for 87604I is: 5495
TABLE 8. θ
JA
VS. AIR FLOW T ABLE FOR 28 LEAD TSSOP
θ
JA
by Velocity (Linear Feet per Minute)
RELIABILITY INFORMATION
0 1 2.5
Multi-Layer PCB, JEDEC Standard Test Boards 64.5°C/W 60.4°C/W 58.5°C/W
PACKAGE OUTLINE - G SUFFIX FOR 28 LEAD TSSOP
TABLE 9. PACKAGE DIMENSIONS
Reference Document: JEDEC Publication 95, MO-153
SYMBOL
Millimeters
Minimum Maximum
N28
A -- 1.20
A1 0.05 0.15
A2 0.80 1.05
b 0.19 0.30
c 0.09 0.20
D 9.60 9.80
E 8.10 BASIC
E1 6.00 6.20
e 0.65 BASIC
L 0.45 0.75
α
aaa -- 0.10
PACKAGE OUTLINE AND PACKAGE DIMENSIONS
REVISION B 11/11/15
87604I DATA SHEET
11 Low Voltage/Low Skew, 1:4 PCI/PCI-X
Zero Delay Clock Generator
TABLE 10. ORDERING INFORMATION
Part/Order Number Marking Package Shipping Packaging Temperature
87604AGILF ICS87604AGILF 28 Lead “Lead-Free” TSSOP tube -40°C to 85°C
87604AGILFT ICS87604AGILF 28 Lead “Lead-Free” TSSOP tape & reel -40°C to 85°C
NOTE: Parts that are with an “LF” suffi x to the part number are the Pb-Free confi guration and are RoHS compliant.
Low Voltage/Low Skew, 1:4 PCI/PCI-X
Zero Delay Clock Generator
87604I DATA SHEET
12 REVISION B 11/11/15
REVISION HISTORY SHEET
Rev Table Page Description of Change Date
A
T7A & T7B 5 AC Characteristics Tables - corrected note sequence.
3/18/05
A
10 10 Ordering Information Table - added marking.
4/12/05
B
T5
T9
1
5
6
8
10
Pin Assignment and General Description - corrected package dimension.
Crystal Characteristics - added Drive Level.
Updated Output Load AC Test Circuit Diagrams.
Application Information - added LVCMOS to XTAL Interface and Recommendations
for Unused Input and Output Pins sections.
Package Dimensions - corrected “E” and “E1” dimensions.
3/8/06
B
T9
1
10
Pin Assignment and General Description - corrected package dimension.
Package Dimensions - corrected “E” and “E1” dimensions.
8/18/06
B
4
9
10
Absolute Maximum Ratings - updated Package Thermal Impedance.
Added Schematic Layout.
Reliability Information - updated Package Thermal Impedance.
1/11/08
B
T7A
T10
1
5
8
11
Pin Assignment, corrected 173-MIL to 240-MIL.
AC Characteristics Table, added Thermal Note.
Updated the Overdriving the Crystal Interface section.
Ordering Information Table - deleted “ICS” prefi x from Part/Order Number column.
Added new Header/Footer in datasheet.
4/1/10
B
T10 11 Ordering Information - removed leaded devices.
Updated data sheet format.
11/11/15

87604AGILFT

Mfr. #:
Manufacturer:
IDT
Description:
Clock Generators & Support Products 4 LVCMOS OUT CLOCK GEN
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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