REVISION B 11/11/15
87604I DATA SHEET
7 Low Voltage/Low Skew, 1:4 PCI/PCI-X
Zero Delay Clock Generator
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
FIGURE 1. POWER SUPPLY FILTERING
10Ω
V
DDA
10μF
.01μF
3.3V
.01μF
V
DD
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. To achieve optimum jitter per-
formance, power supply isolation is required. The 87604I pro-
vides separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V
DD
, V
DDA
, and
V
DDO
should be individually connected to the power supply
plane through vias, and 0.01μF bypass capacitors should be
used for each pin. Figure 1 illustrates this for a generic V
DD
pin
and also shows that V
DDA
requires that an additional10Ω resistor
along with a 10µF bypass capacitor be connected to the V
DDA
pin.
The 10Ω resistor can also be replaced by a ferrite bead.
INPUTS:
CRYSTAL INPUT
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left fl oating. Though not
required, but for additional protection, a 1kΩ resistor can be tied
from XTAL_IN to ground.
REF_CLK INPUT
For applications not requiring the use of the reference clock, it can
be left fl oating. Though not required, but for additional protection, a
1kΩ resistor can be tied from the REF_CLK to ground.
LVCMOS CONTROL PINS
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional protection.
A 1kΩ resistor can be used.
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
OUTPUTS:
LVCMOS OUTPUTS
All unused LVCMOS output can be left fl oating. There should be
no trace attached.
CRYSTAL INPUT INTERFACE
The 87604I has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown in Figure
2 below were determined using a 25MHz, 18pF parallel resonant
crystal and were chosen to minimize the frequency ppm error. The
optimum C1 and C2 values can be slightly adjusted for optimum
frequency accuracy.
FIGURE 2. CRYSTAL INPUt INTERFACE
XTAL_IN
XTAL_OUT
X1
18pF Parallel Crystal
C1
22pF
C2
22pF
