REV. A
AD7709
–11–
ADC CIRCUIT INFORMATION
Overview
The AD7709 incorporates a ⌺-⌬ ADC channel with on-chip digital
filtering intended for the measurement of wide dynamic range, low
frequency signals such as those in weigh-scale, strain-gauge,
pressure transducer, or temperature measurement applications.
⌺-⌬ ADC
This channel can be programmed to have one of eight input
voltage ranges from ± 20 mV to ±2.56 V. This channel can be
configured as either two fully differential inputs (AIN1/AIN2
and AIN3/AIN4) or four pseudo-differential input channels
(AIN1/AINCOM, AIN2/AINCOM, AIN3/AINCOM, and
AIN4/AINCOM). Buffering the input channel means that the
part can accommodate significant source impedances on the
analog input and that R, C filtering (for noise rejection or RFI
reduction) can be placed on the analog inputs if required.
The ADC employs a ⌺-⌬ conversion technique to realize up to
16 bits of no-missing-codes performance. The ⌺-⌬ modulator
converts the sampled input signal into a digital pulse train whose
duty cycle contains the digital information. A Sinc
3
programmable
low-pass filter is then employed to decimate the modulator output
data stream to give a valid data conversion result at programmable
output rates from 5.35 Hz (186.77 ms) to 105.03 Hz (9.52 ms).
A chopping scheme is also employed to minimize ADC channel
offset errors. A block diagram of the ADC input channel is shown
in Figure 4.
The sampling frequency of the modulator loop is many times
higher than the bandwidth of the input signal. The integrator in
the modulator shapes the quantization noise (which results from
the analog-to-digital conversion) so that the noise is pushed
toward one-half of the modulator frequency. The output of the
⌺-⌬ modulator feeds directly into the digital filter. The digital
filter then band-limits the response to a frequency significantly
lower than one-half of the modulator frequency. In this manner,
the 1-bit output of the comparator is translated into a band-
limited, low noise output from the AD7709 ADC. The AD7709
filter is a low-pass, Sinc
3
, or (SIN(x)/x)
3
filter whose primary
function is to remove the quantization noise introduced at the
modulator. The cutoff frequency and decimated output data
rate of the filter are programmable via the SF word loaded to the
filter register.
A chopping scheme is employed where the complete signal chain
is chopped, resulting in excellent dc offset and offset drift speci-
fications, and is extremely beneficial in applications where drift,
noise rejection, and optimum EMI rejection are important fac-
tors. With chopping, the ADC repeatedly reverses its inputs.
The decimated digital output words from the Sinc
3
filters there-
fore have a positive offset and negative offset term included. As a
result, a final summing stage is included so that each output
word from the filter is summed and averaged with the previous
filter output to produce a new valid output result to be written to
the ADC data register.
The input chopping is incorporated into the input multiplexer
while the output chopping is accomplished by an XOR gate at
the output of the modulator. The chopped modulator bit stream
is applied to a Sinc
3
filter. The programming of the Sinc
3
deci-
mation factor is restricted to an 8-bit register SF, the actual
decimation factor is the register value × 8. The decimated out-
put rate from the Sinc
3
filter (and the ADC conversion rate) will
therefore be:
f
SF
f
ADC MOD
=×
×
×
1
3
1
8
where:
f
ADC
is the ADC update rate.
SF is the decimal equivalent of the word loaded to the
filter register.
f
MOD
is the modulator sampling rate of 32.768 kHz.
Programming the filter register determines the update rate for the
ADC. The chop rate of the channel is half the output data rate.
The frequency response of the filter H(f ) is as follows:
1
8
8
1
2
2
3
SF
SF f / f
f/f
f/f
f/f
MOD
MOD
OUT
OUT
×
×
×××
×
×
×
××
×
sin ( )
sin ( )
sin ( )
sin ( )
π
π
π
π
where:
f
MOD
= 32,768 Hz.
SF = value programmed into Filter Register.
f
OUT
= f
MOD
/(SF ⫻ 8 ⫻ 3)
The following shows plots of the filter frequency response for the
SF words shown in Table I. The overall frequency response is the
product of a Sinc
3
and a sinc response. There are Sinc
3
notches
at integer multiples of 3 ⫻ f
ADC
, and there are sinc notches at odd
integer multiples of f
ADC
/2. The 3 dB frequency for all values of SF
obeys the following equation:
fdB f
ADC
3024
()
=×.
The signal chain is chopped as shown in Figure 4. The chop
frequency is:
f
f
CHOP
ADC
=
2
SINC
3
FILTER
MUX
BUF
PGA
⌺-⌬
MOD
XOR
ANALOG
INPUT
DIGITAL
OUTPUT
1
8 ⴛ SF
⌺
3
(
(8 ⴛ SF )
3 ⴛ
⌺
1
2
A
IN
+ V
OS
A
IN
– V
OS
f
CHOP
f
IN
f
MOD
f
CHOP
f
ADC
)
Figure 4. ADC Channel Block Diagram
