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AD7709ARUZ-REEL7

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33
REV. A
AD7709
–6–
TIMING CHARACTERISTICS
1, 2
Limit at T
MIN
, T
MAX
Parameter (A, B Version) Unit Conditions/Comments
t
1
30.5176
ms
typ Crystal Oscillator Period
t
2
50 ns min RESET Pulsewidth
Read Operation
t
3
0 ns min RDY to CS Setup Time
t
4
0 ns min CS Falling Edge to SCLK Active Edge Setup Time
3
t
5
4
0 ns min SCLK Active Edge to Data Valid Delay
3
60 ns max V
DD
= 4.75 V to 5.25 V
80 ns max V
DD
= 2.7 V to 3.6 V
t
5A
4, 5
0 ns min CS Falling Edge to Data Valid Delay
60 ns max V
DD
= 4.75 V to 5.25 V
80 ns max V
DD
= 2.7 V to 3.6 V
t
6
100 ns min SCLK High Pulsewidth
t
7
100 ns min SCLK Low Pulsewidth
t
8
0 ns min CS Rising Edge to SCLK Inactive Edge Hold Time
3
t
9
6
10 ns min Bus Relinquish Time after SCLK Inactive Edge
3
80 ns max
t
10
100 ns max SCLK Active Edge to RDY High
3, 7
Write Operation
t
11
0 ns min CS Falling Edge to SCLK Active Edge Setup Time
3
t
12
30 ns min Data Valid to SCLK Edge Setup Time
t
13
25 ns min Data Valid to SCLK Edge Hold Time
t
14
100 ns min SCLK High Pulsewidth
t
15
100 ns min SCLK Low Pulsewidth
t
16
0 ns min CS Rising Edge to SCLK Edge Hold Time
NOTES
1
Sample tested during initial release to ensure compliance. All input signals are specified with t
R
= t
F
= 5 ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6 V.
2
See Figures 2 and 3.
3
SCLK active edge is falling edge of SCLK.
4
These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross the V
OL
or V
OH
limits.
5
This specification comes into play only if CS goes low while SCLK is low. It is required primarily for interfacing to DSP machines.
6
These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapo-
lated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the Timing Characteristics table are the true bus relinquish
times of the part and as such are independent of external bus loading capacitances.
7
RDY returns high after a read of the ADC. The same data can be read again, if required, while RDY is high, although care should be taken that subsequent reads do not occur
close to the next output update.
(V
DD
= 2.7 V to 3.6 V or V
DD
= 4.75 V to 5.25 V; GND = 0 V; X
TAL
= 32.768 kHz; Input Logic 0 = 0 V,
Logic 1 = V
DD
unless otherwise noted.)
REV. A
AD7709
–7–
I
SINK
(1.6mA WITH V
DD
= 5V
100A WITH V
DD
= 3V)
1.6V
I
SOURCE
(200A WITH V
DD
= 5V
100A WITH V
DD
= 3V)
TO OUTPUT
PIN
50pF
Figure 1. Load Circuit for Timing Characterization
t
12
t
13
t
14
t
15
t
11
t
16
MSB
LSB
CS
SCLK
DIN
Figure 2. Write Cycle Timing Diagram
t
5
t
5A
t
4
t
6
t
3
t
9
MSB
LSB
CS
SCLK
t
8
t
10
t
7
DOUT
RDY
Figure 3. Read Cycle Timing Diagram
REV. A
AD7709
–8–
WARNING!
ESD SENSITIVE DEVICE
PIN CONFIGURATION
TOP VIEW
(Not to Scale)
1
AD7709
GND
V
DD
XTAL2
XTAL1
RDY
DOUT
DIN
RESET
SCLK
CS
P1/SW1
PWRGND
IOUT1
IOUT2
REFIN1(+)
REFIN1(–)
AIN1
AIN2
AIN3/P3
AIN4/P4
AINCOM
P2/SW2
REFIN2(+)
REFIN2(–)
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
ABSOLUTE MAXIMUM RATINGS*
(T
A
= 25∞C, unless otherwise noted.)
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
PWRGND to AGND . . . . . . . . . . . . . . –20 mV to +20 mV
Analog Input Voltage to GND . . . . . –0.3 V to V
DD
+ 0.3 V
Reference Input Voltage to GND . . . –0.3 V to V
DD
+ 0.3 V
Total AIN/REFIN Current (Indefinite) . . . . . . . . . . 30 mA
Digital Input Voltage to GND . . . . . . . –0.3 V to V
DD
+ 0.3 V
Digital Output Voltage to GND . . . . –0.3 V to V
DD
+ 0.3 V
Operating Temperature Range . . . . . . . . . . –40∞C to +85∞C
Storage Temperature Range . . . . . . . . . . . . –65∞C to +150∞C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150∞C
q
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . 97.9∞C/W
q
JC
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 14∞C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215∞C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220∞C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ORDERING GUIDE
Temperature Package Package
Model Range Description Option
AD7709ARU –40∞C to +85∞C TSSOP RU-24
AD7709BRU –40∞C to +85∞C TSSOP RU-24
EVAL-AD7709EB Evaluation Board
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD7709 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33

AD7709ARUZ-REEL7

Mfr. #:
Buy AD7709ARUZ-REEL7
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 16-Bit w/ Current Sources
Lifecycle:
New from this manufacturer.
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