REV. A
AD7709
–18–
Table VIII. Filter Register Bit Designations
Table IX. Update Rate vs. SF WORD
SF (Dec) SF (Hex) f
ADC
(Hz) t
ADC
(ms)
13 0D 105.3 9.52
69 45 19.79 50.34
255 FF 5.35 186.77
Table VII. Configuration Register Bit Designations (continued)
Bit Bit
Location Name Description
CONFIG3 UNI Unipolar/Bipolar Operation Selection Bit.
Set by the user to enable unipolar operation. In this mode, the device uses straight binary output coding
i.e., 0 differential input will generate a result of 0000h and a full-scale differential input will generate a
code of FFFFh.
Cleared by the user to enable pseudo-bipolar operation. The device uses offset binary coding, i.e., a nega-
tive full-scale differential input will result in a code of 0000h, a 0 differential input will generate a code of
8000h, while a positive full-scale differential input will result in a code of FFFFh.
CONFIG2 RN2 This bit is used in conjunction with RN1 and RN0 to select the analog input range as shown below.
CONFIG1 RN1 This bit is used in conjunction with RN2 and RN0 to select the analog input range as shown below.
CONFIG0 RN0 This bit is used in conjunction with RN2 and RN1 to select the analog input range as shown below.
Filter Register (A1, A0 = 1, 0; Power-On-Reset = 45h)
The Filter Register is an 8-bit register from which data can be
read or to which data can be written. This register determines
the amount of averaging performed by the sinc filter. Table VIII
outlines the bit designations for the Filter Register. FR7 through
FR0 indicate the bit location, FR denoting the bits are in the
Filter Register. FR7 denotes the first bit of the data stream. The
number in brackets indicates the power-on/reset default status
of that bit. The number in this register is used to set the decima-
tion factor and thus the output update rate for the ADC. The
Filter Register cannot be written to by the user while the ADC
is active. The update rate is calculated as follows:
f
SF
f
ADC MOD
¥
¥
1
3
1
8
where:
f
ADC
is the ADC output update rate.
f
MOD
is the Modulator Clock Frequency = 32.768 kHz.
SF is the decimal value written to the SF Register.
The allowable range for SF is 13dec to 255dec. Examples of SF
values and corresponding conversion rate (f
ADC
) and time (t
ADC
)
are shown in Table IX. It should also be noted that the ADC
input channel is chopped to minimize offset errors. This means
that the time for a single conversion or the time to the first con-
version result is 2 t
ADC
.
ADC Data Result Register (A1, A0 = 1, 1; Power-On-Reset =
0000h)
The conversion result is stored in the ADC Data Register (DATA).
This register is 16-bits wide. This is a read-only register. On
completion of a read from this register, the RDY bit in the
Status Register is cleared.
7RF6RF5RF4RF3RF2RF1RF0RF
)0(7FS)1(6FS)0(5FS)0(4FS)0(3FS)1(2FS)0(1FS)1(0FS
RN2 RN1 RN0 Selected ADC Input Range (V
REF
= 2.5 V)
00 0 ± 20 mV
00 1 ± 40 mV
01 0 ± 80 mV
01 1 ± 160 mV
10 0 ± 320 mV
10 1 ± 640 mV
11 0 ± 1.28 V
11 1 ± 2.56 V
REV. A
AD7709
–19–
CONFIGURING THE AD7709
The four user-accessible registers on the AD7709 are accessed via
the serial interface. Communication with any of these registers
is initiated by first writing to the Communications Register. The
AD7709 begins converting on power-up without the need to
write to
the registers. The default conditions are used, i.e., the
AD7709 operates at a 19.79 Hz update rate that offers 50 Hz
and 60 Hz rejection.
Figure 10 outlines a flow diagram of the sequence used to
configure all registers after a power-up or reset on the AD7709.
The flowchart shows two methods of determining when it is valid
to read the data register. The first method is hardware polling of
the RDY pin and the second method involves software interrogation
of the RDY bit in the status register. The flowchart details all the
necessary programming steps required to initialize the ADC and
read data from the ADC channel following a power-on or reset.
The steps can be broken down as follows:
1. Configure and initialize the microcontroller or microproces-
sor serial port.
2. Initialize the AD7709 by configuring the following registers:
a)
Filter Register to configure the update rate for the channel.
The AD7709 must be placed in standby mode before the
Filter Register can be written to.
b)Configuration Register to select the input channel to be
converted, its input range, and reference. This register is also
used to configure internal current sources, power switches,
and I/O port.
Both of these operations consist of a write to the Communi-
cations Register to specify the next operation as a write to a
specified register. Data is then written to this register. When
each sequence is complete, the ADC defaults to waiting for
another write to the Communications Register to specify the
next operation.
3. When configuration is complete, the user needs to determine
when it is valid to read the data from the data register. This is
accomplished either by polling the RDY pin (hardware polling)
or by interrogating the RDY bit in the STATUS register
(software
polling). Both are shown in Figure 10.
POLL RDY PIN
HARDWARE
POLLING
START
SOFTWARE
POLLING
POWER-ON-RESET FOR AD7709
CONFIGURE AND INITIALIZE C/P SERIAL PORT
WRITE TO COMMUNICATIONS REGISTER SETTING
UP NEXT OPERATION TO BE A WRITE TO THE
FILTER REGISTER (WRITE 22H TO REGISTER)
WRITE TO FILTER REGISTER CONFIRMING
THE REQUIRED UPDATE RATE
WRITE TO COMMUNICATIONS REGISTER SETTING
UP NEXT OPERATION TO BE A WRITE TO THE
CONFIGURATION REGISTER
(WRITE 01H TO REGISTER)
READ DATA FROM OUTPUT REGISTER
WRITE TO COMMUNICATIONS REGISTER SETTING
UP NEXT OPERATION TO BE A READ FROM THE
STATUS REGISTER (WRITE 40H TO REGISTER)
WRITE TO COMMUNICATIONS REGISTER SETTING
UP NEXT OPERATION TO BE A READ FROM THE
DATA REGISTER (WRITE 43H TO REGISTER)
WRITE TO COMMUNICATIONS REGISTER SETTING
UP NEXT OPERATION TO BE A READ FROM THE
DATA REGISTER (WRITE 43H TO REGISTER)
READ 16-BIT DATA RESULT
READ 16-BIT DATA RESULT
READ STATUS REGISTER
ANOTHER
READ
RDY
LOW?
ANOTHER
READ
CHANNEL
CHANGE
RDY = 1
END
END
SOFTWARE
POLLING
HARDWARE
POLLING
NO
YES
YES
YES
NO
YES
NO
YES
NO
YES
NO
WRITE TO CONFIGURATION REGISTER TO SELECT
THE INPUT CHANNEL, INPUT RANGE, AND
REFERENCE. CURRENT SOURCES AND I/O PORT
CAN ALSO BE CONFIGURED
CHANNEL
CHANGE
Figure 10. Flowchart for Initializing and Reading Data from the AD7709
REV. A
AD7709
–20–
DIGITAL INTERFACE
As previously outlined, AD7709 programmable functions are
controlled using a set of on-chip registers. Data is written to
these registers via the part’s serial interface and read access to
the on-chip registers is also provided by this interface. All com-
munications to the part must start with a write operation to the
Communications Register. After power-on or
reset
, the device
expects a write to its Communications Register. The data writ-
ten to this register determines whether the next operation to the
part is a read or a write operation and also determines to which
register this read or write operation occurs. Therefore, write
access to any of the other registers on the part starts with a write
operation to the Communications Register followed by a write
to the selected register. A read operation from any other register
on the part (including the output data register) starts with a
write operation to the Communications Register followed by a
read operation from the selected register.
The AD7709 serial interface consists of five signals: CS, SCLK,
DIN, DOUT, and RDY. The DIN line is used for transferring
data into the on-chip registers, while the DOUT line is used for
accessing data from the on-chip registers. SCLK is the serial
clock input for the device, and all data transfers (either on DIN
or DOUT) take place with respect to this SCLK signal. The
RDY line is used as a status signal to indicate when data is ready
to be read from the AD7709 data register. RDY goes low when a
new data-word is available in the output register. It is reset high
when a read operation from the data register is complete. It also
goes high prior to the updating
of the output register to indicate
when not to read from the device
to ensure that a data read is not
attempted while the register is being updated. CS is used to select
the device. It can be used to decode the AD7709 in systems where
a number of parts are connected to the serial bus.
Figures 2 and 3 show timing diagrams for interfacing to the
AD7709 with CS used to decode the part. Figure 3 is for a read
operation from the AD7709 output shift register while Figure 2
shows a write operation to the input shift register. It is possible
to read the same data twice from the output register even though
the RDY line returns high after the first read operation. Care must
be taken, however, to ensure that the read operations have been
completed before the next output update is about to take place.
The AD7709 serial interface can operate in 3-wire mode by
tying the CS input low. In this case, the SCLK, DIN, and
DOUT lines are used to communicate with the AD7709, and
the status of the RDY bit can be obtained by interrogating the
Status Register. This scheme is suitable for interfacing to
microcontrollers. If CS is required as a decoding signal, it can
be generated from a port bit. For microcontroller interfaces, it is
recommended that the SCLK idles high between data transfers.
The AD7709 can also be operated with CS used as a frame
synchronization signal. This scheme is suitable for DSP interfaces.
In this case, the first bit (MSB) is effectively clocked out by CS
since CS would normally occur after the falling edge of SCLK
in DSPs. The SCLK can continue to run between data transfers
provided the timing numbers are obeyed.
The serial interface can be reset by exercising the RESET input
on the part. It can also be reset by writing a series of 1s on the
DIN input. If a Logic 1 is written to the AD7709 DIN line for
at least 32 serial clock cycles, the serial interface is reset. This
ensures that in 3-wire systems, if the interface gets lost either via
a software error or by some glitch in the system, it can be reset
back to a known state. This state returns the interface to where
the AD7709 is expecting a write operation to its Communications
Register. This operation resets the contents of all registers to their
power-on reset values.
Some microprocessor or microcontroller serial interfaces have a
single serial data line. In this case, it is possible to connect the
AD7709 DOUT and DIN lines together and connect them to the
single data line of the processor. A 10 kW pull-up resistor should
be used on this single data line. In this case, if the interface gets
lost, because the read and write operations share the same line,
the procedure to reset it back to a known state is somewhat
different than previously described. It requires a read operation
of 24 serial clocks followed by a write operation where a Logic 1
is written for at least 32 serial clock cycles to ensure that the
serial interface is back into a known state.
MICROCOMPUTER/MICROPROCESSOR INTERFACING
The AD7709 flexible serial interface allows for easy interface to
most microcomputers and microprocessors. The flowchart of
Figure 10 outlines the sequence that should be followed when
interfacing a microcontroller or microprocessor to the AD7709.
Figures 11, 12, and 13 show some typical interface circuits. The
serial interface on the AD7709 is capable of operating from just
three wires and is compatible with SPI interface protocols. The
3-wire operation makes the part ideal for isolated systems where
minimizing the number of interface lines minimizes the number
of opto-isolators required in the system. The serial clock input is
a Schmitt-triggered input to accommodate slow edges from
opto-couplers. The rise and fall times of other digital inputs to
the AD7709 should be no longer than 1 ms.
Some of the registers on the AD7709 are 8-bit registers, which
facilitates easy interfacing to the 8-bit serial ports of microcon-
trollers. The Data Register on the AD7709 is 16 bits and the
Configuration Register is 24 bits, but data transfers to these
registers can consist of multiple 8-bit transfers to the serial port
of the microcontroller. DSP processors and microprocessors
generally transfer 16 bits of data in a serial data operation. Some
of these processors, such as the ADSP-2105, have the facility to
program the amount of cycles in a serial transfer. This allows the
user to tailor the number of bits in any transfer to match the
register length of the required register in the AD7709.
Even though some of the registers on the AD7709 are only 8 bits
in length, communicating with two of these registers in successive
write operations can be handled as a single 16-bit data transfer if
required. For example, if the Filter Register is to be updated, the
processor must first write to the Communications Register (say-
ing that the next operation is a write to the Filter Register), and
then write 8 bits to the Filter Register. If required, this can all be
done in a single 16-bit transfer because once the eight serial
clocks of the write operation to the Communications Register
have been completed, the part immediately sets itself up for a
write operation to the Filter Register.

AD7709BRUZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 16-Bit w/ Current Sources
Lifecycle:
New from this manufacturer.
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